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73s1217f bus-powered 80515 system-on-chip with usb, iso 7816 / emv, pinpad and more simplifying system integration? data sheet december 2008 rev. 1.2 ? 2008 teridian semiconductor corporation 1 general description the teridian semiconductor corporation 73s1217f is a versatile and economical cmos system-on-chip device intended for smart card reader applications. the circuit features an iso-7816 / emv interface, an usb 2.0 interface (full-speed 12mbps - slave) and a 5x6 pinpad interface. additional features include 8 user i/os, multiple interrupt options and an analog voltage input (for dc voltage monitoring such as battery level detection). other built-in interfaces include an asynchronous serial and an i 2 c interface. the system-on-chip is built around an 80515 high- performance core. its feature and instruction set is compatible with the i ndustry standard 8051, while offering one clock-cycle per instruction processing power (most instructions). with a cpu clock running up to 24mhz, it results in up to 20mips available that meets the requirements of various encryption needs such as aes, des / 3-des and even rsa (for pin encryption for instance). the circuit requires a single 6 to 12 mhz crystal. an optional 32khz crystal can be connected to a sub-system oscillator with a real-time- clock counter to enable stand-alone applications to access an rtc value. the respective 73s1217f embedded memories are; 64kb flash program memory, 2kb user xram memory, and 256b iram memory. on top of these memories are added independent fifos dedicated to the iso7816 uart and to the usb interface. the chip incorporates an inductor-based dc-dc converter that generates all the necessary voltages to the various 73s1217f function blocks (smart card interface, digital core, etc. ) from any of two distinct power supply sources: the +5v usb bus (v bus , 4.4v to 6.5v), or a main battery (v bat , 4.0v to 6.5v). the chip automatically powers-up t he dc-dc converter with v bus if it is present, or uses v bat as the supply input. alternatively, the pin v pc can support a wider power supply input range (2.7v to 6.5v), when using a single system supply source. in addition, the circuit f eatures an on/off mode which operates directly with an on/off system switch: any activity on the on/off button is debounced internally and controls the power generation circuit accordingly, under the supervision of the firmware (off request / off acknowledgement at firmware level). the off mode can be alternatively init iated from the controller (firmware action instead of on/off switch). in off mode, the circuit typically draws less than 1 a, which makes it ideal for applications where battery life must be maximized. wake-up of the controller upon usb cable insertion is supported. embedded flash memory is in-system programmable and lockable by means of on-silicon fuses. this makes the teridian 73s1217f suitabl e for both development and production phases. teridian semiconductor corporation offers with its 73s1217f a very comprehensive set of software libraries, including the smart card and usb protocol layers that are pre-approved against usb, microsoft whql and emv, as well as a ccid reference design. refer to the teridian semiconductor corporation 73s12xxf software users guide for a complete description of the application programming interface (api libraries) and related software modules. a complete array of development and programming tools, libraries and demonstration boards enable rapid development and certif ication of readers that meet most demanding smart card standards. applications ? hand-held pinpad smart card readers: ? with usb or serial connectivity ? ideal for e-banking (masterca rd cap, etc) and digital identification (secure login, govt id...) ? transparent usb card readers and usb keys ? general purpose smart card readers advantages ? reduced bom ? larger built-in flash / ram than its competitors ? higher performance cpu core (up to 24mips) ? on-chip dc-dc converter and cmos switches for battery and usb power ? sub- a power down mode with on/off switch ? powerful in-circuit emulation and programming ? a complete set of emv4.1, usb and ccid libraries ? overall, the ideal compromise cost / features for high volume, pinpad reader applications! downloaded from: http:///
73s1217f data sheet ds_1217f_001 2 rev. 1.2 features 80515 core: ? 1 clock cycle per instruction (most instructions) ? cpu clocked up to 24mhz ? 64kb flash memory (lockable) ? 2kb xram (user data memory) ? 256 byte iram ? hardware watchdog timer oscillators: ? single low-cost 6mhz to 12mhz crystal ? optional 32khz crystal (with internal rtc) ? an internal pll provides all the necessary clocks to each block of the system interrupts: ? standard 80c515 4-priority level structure ? 9 different sources of interrupt to the core power down modes: ? 2 standard 80c515 power down and idle modes ? sub- a off mode on/off main system power switch: ? input for an spst momentary switch to ground timers: ? (2) standard 80c52 timers t0 and t1 ? (1) 16-bit timer that can generate rtc interrupts from the 32khz clock built-in iso-7816 card interface: ? ldo regulator produces vcc for the card ? (1.8v, 3v or 5v) ? full compliance with emv 4.1 ? activation/deactivation sequencers ? auxiliary i/o lines (c4-c8 signals) ? 7kv esd protection on all interface pins communication with smart cards: ? iso 7816 uart for t=0, t=1 ? (2) 2-byte fifos for transmit and receive ? configured to drive multiple external teridian 73s8010xx interfaces (for mu lti-sam architectures) communication interfaces: ? full-duplex serial interface (1200 to 115kbps uart) ? usb 2.0 full speed 12mbps interface, pc/sc compliant with 4 endpoints: ? control (16b fifo) ? interrupt in (32b fifo) ? bulk in (128b fifo) ? bulk out (128b fifo) ? i 2 c master interface (400kbps) man-machine interface and i/os: ? 6x5 keyboard (hardware scanning, debouncing and scrambling) ? (8) user i/os ? single programmable current output (led) voltage detection: ? analog input (detection range: 1.0v to 1.5v) operating voltage: ? single supply 2.7v to 6.5v operation (vpc) ? usb supply (vbus 4.4v to 5.5v) with or without battery back up operation (vbat 4.0v to 6.5v). ? automated detection of vo ltage presence - priority on vbus over vbat dc-dc converter: ? step-up converter ? generates an intermediary voltage vp ? requires a single 10 h inductor ? 3.3v supply available for external circuits operating temperature: ? -40c to 85c package: ? 68-pin qfn software: ? two-level application programming interface (ansi c-language libraries) ? usb, t=0 / t=1 iso and emv compliant smart card protocol layers ? ccid reference design and windows ? driver downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 3 table of contents 1 ? hardware description ......................................................................................................................... 8 ? 1.1 ? pin description .............................................................................................................................. 8 ? 1.2 ? hardware overview .................................................................................................................... 11 ? 1.3 ? 80515 mpu core ........................................................................................................................ 11 ? 1.3.1 ? 80515 overview ............................................................................................................. 11 ? 1.3.2 ? memory organization .................................................................................................... 11 ? 1.4 ? program security ........................................................................................................................ 16 ? 1.5 ? special function registers (sfrs) ............................................................................................ 18 ? 1.5.1 ? internal data special function registers (sfrs) .......................................................... 18 ? 1.5.2 ? iram special function registers (generic 80515 sfrs) ............................................ 19 ? 1.5.3 ? external data special function registers (sfrs) ........................................................ 20 ? 1.6 ? instruction set ............................................................................................................................. 23 ? 1.7 ? peripheral descriptions ............................................................................................................... 23 ? 1.7.1 ? oscillator and clock generation .................................................................................... 23 ? 1.7.2 ? power supply management .......................................................................................... 26 ? 1.7.3 ? power on/off .............................................................................................................. 27 ? 1.7.4 ? power control modes .................................................................................................... 28 ? 1.7.5 ? interrupts ........................................................................................................................ 35 ? 1.7.6 ? uart ............................................................................................................................. 42 ? 1.7.7 ? timers and counters ..................................................................................................... 47 ? 1.7.8 ? wd timer (software watchdog timer) ......................................................................... 49 ? 1.7.9 ? user (usr) ports ........................................................................................................... 52 ? 1.7.10 ? real-time clock with hardware watchdog (rtc) ........................................................ 54 ? 1.7.11 ? analog voltage comparator .......................................................................................... 57 ? 1.7.12 ? led driver ..................................................................................................................... 59 ? 1.7.13 ? i 2 c master interface ....................................................................................................... 60 ? 1.7.14 ? keypad interface ............................................................................................................ 67 ? 1.7.15 ? emulator port ................................................................................................................. 74 ? 1.7.16 ? usb interface ................................................................................................................ 75 ? 1.7.17 ? smart card interface function ...................................................................................... 78 ? 1.7.18 ? vdd fault detect function .......................................................................................... 113 ? 2 ? application schematics ................................................................................................................. 114 ? 2.1 ? typical application schematic 1 ............................................................................................... 114 ? 2.2 ? typical application schematic 2 ............................................................................................... 115 ? 3 ? electrical specification ................................................................................................................... 116 ? 3.1 ? absolute maximum ratings ...................................................................................................... 116 ? 3.2 ? recommended operating conditions ...................................................................................... 116 ? 3.3 ? digital io characteristics .......................................................................................................... 117 ? 3.4 ? oscillator interface requirements ............................................................................................ 118 ? 3.5 ? dc characteristics: analog input ............................................................................................. 118 ? 3.6 ? usb interface requirements .................................................................................................... 119 ? 3.7 ? smart card interface requirements ......................................................................................... 121 ? 3.8 ? dc characteristics .................................................................................................................... 123 ? 3.9 ? current fault detection circuits ............................................................................................... 125 ? 4 ? equivalent circuits ......................................................................................................................... 126 ? 4.1 ? package pin designation (68-pin qfn) ................................................................................... 135 ? 4.2 ? packaging information .............................................................................................................. 136 ? 5 ? ordering information ...................................................................................................................... 137 ? 6 ? related documentation .................................................................................................................. 137 ? 7 ? contact information ........................................................................................................................ 137 ? revision history .............................................................................................................................. ........ 138 ? downloaded from: http:///
73s1217f data sheet ds_1217f_002 figures figure 1: ic functional block diagram ......................................................................................................... 7 ? figure 2: memory map .............................................................................................................................. .. 15 ? figure 3: clock generation and control circuits ........................................................................................ 23 ? figure 4: oscillator circuit ........................................................................................................................... 25 ? figure 5: detailed power management logic block diagram .................................................................... 26 ? figure 6: power-down control .................................................................................................................... 29 ? figure 7: detail of power-down interrupt logic .......................................................................................... 30 ? figure 8: power-down sequencing ............................................................................................................ 30 ? figure 9: external interrupt configuration ................................................................................................... 35 ? figure 10: real time clock block diagram ................................................................................................ 54 ? figure 11: i 2 c write mode operation .......................................................................................................... 61 ? figure 12: i 2 c read operation ................................................................................................................... 62 ? figure 13: simplified keypad block diagram ............................................................................................. 67 ? figure 14: keypad interface flow chart ..................................................................................................... 69 ? figure 15: usb block diagram ................................................................................................................... 75 ? figure 16: smart card interface block diagram ......................................................................................... 78 ? figure 17: smart card interface block diagram ......................................................................................... 79 ? figure 18: asynchronous activation sequence timing .............................................................................. 81 ? figure 19: deactivation sequence .............................................................................................................. 82 ? figure 20: smart card clk and etu generation ...................................................................................... 83 ? figure 21: guard, block, wait and atr time definitions .......................................................................... 84 ? figure 22: synchronous activation ............................................................................................................. 86 ? figure 23: example of sync mode oper ation: generating/reading atr signals ..................................... 86 ? figure 24: creation of synchronous clock start/stop mode start bit in sync mode ................................. 87 ? figure 25: creation of synchronous clock start/stop mode stop bit in sync mode ................................. 87 ? figure 26: operation of 9-bit mode in sync mode ...................................................................................... 88 ? figure 27: 73s1217f typical application schem atic (handheld usb pinpad, with combo usb- bus and self-powered configuration) ..................................................................................... 114 ? figure 28: 73s1217f typical application sc hematic (usb transparent reader and usb key configuration) .......................................................................................................................... 115 ? figure 29: 12 mhz oscillator circuit ......................................................................................................... 126 ? figure 30: 32khz oscillator circuit ........................................................................................................... 126 ? figure 31: digital i/o circuit ...................................................................................................................... 127 ? figure 32: digital output circuit ................................................................................................................ 127 ? figure 33: digital i/o with pull up circuit .................................................................................................. 128 ? figure 34: digital i/o with pull down circuit ............................................................................................. 128 ? figure 35: digital input circuit ................................................................................................................... 129 ? figure 36: off_req interface circuit ..................................................................................................... 129 ? figure 37: keypad row circuit ................................................................................................................. 130 ? figure 38: keypad column circuit ............................................................................................................ 130 ? figure 39: led circuit .............................................................................................................................. . 131 ? figure 40: test and security pin circuit ................................................................................................... 131 ? figure 41: analog input circuit ................................................................................................................. 132 ? figure 42: smart card output circuit ....................................................................................................... 132 ? figure 43: smart card i/o circuit ............................................................................................................. 133 ? figure 44: pres input circuit ................................................................................................................... 133 ? figure 45: usb circuit .............................................................................................................................. 134 ? figure 46: on_off input circuit .............................................................................................................. 134 ? figure 47: 73s1217f pinout ..................................................................................................................... 135 ? figure 48: 73s1217f 68 qfn mechanical drawing ................................................................................. 136 ? 4 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 5 tables table 1: 73s1217 pinout description ........................................................................................................... 8 ? table 2: mpu data memory map ............................................................................................................... 11 ? table 3: flash special function registers ................................................................................................. 13 ? table 4: internal data memory map ........................................................................................................... 14 ? table 5: program security registers .......................................................................................................... 17 ? table 6: iram special function registers locations ................................................................................ 18 ? table 7: iram special function registers reset values .......................................................................... 19 ? table 8: xram special function registers reset values ......................................................................... 20 ? table 9: psw register flags ...................................................................................................................... 22 ? table 10: port registers ............................................................................................................................. 22 ? table 11: frequencies and mcount values for mclk = 96mhz ................................................................ 24 ? table 12: the mclkctl register ................................................................................................................ 24 ? table 13: the mpuckctl register ............................................................................................................. 25 ? table 14: the int5ctl register .................................................................................................................. 31 ? table 15: the misctl0 register .................................................................................................................. 31 ? table 16: the misctl1 register .................................................................................................................. 32 ? table 17: the mclkctl register ................................................................................................................ 33 ? table 18: the pcon register .................................................................................................................... 34 ? table 19: the ien0 register ...................................................................................................................... 36 ? table 20: the ien1 register ...................................................................................................................... 37 ? table 21: the ien2 register ...................................................................................................................... 37 ? table 22: the tcon register .................................................................................................................... 38 ? table 23: the t2con register .................................................................................................................. 38 ? table 24: the ircon register ................................................................................................................... 39 ? table 25: external mpu interrupts .............................................................................................................. 39 ? table 26: control bits for external interrupts .............................................................................................. 40 ? table 27: priority level groups .................................................................................................................. 40 ? table 28: the ip0 register ......................................................................................................................... 40 ? table 29: the ip1 register ......................................................................................................................... 41 ? table 30: priority levels .............................................................................................................................. 41 ? table 31: interrupt polling sequence .......................................................................................................... 41 ? table 32: interrupt vectors ......................................................................................................................... 41 ? table 33: uart modes .............................................................................................................................. 42 ? table 34: baud rate generation ................................................................................................................ 42 ? table 35: the pcon register .................................................................................................................... 43 ? table 36: the brcon register ................................................................................................................. 43 ? table 37: the misctl0 register .................................................................................................................. 44 ? table 38: the s0con register .................................................................................................................. 45 ? table 39: the s1con register .................................................................................................................. 46 ? table 40: the tmod register .................................................................................................................... 47 ? table 41: timers/counters mode description ............................................................................................ 48 ? table 42: the tcon register .................................................................................................................... 49 ? table 43: the ien0 register ...................................................................................................................... 50 ? table 44: the ien1 register ...................................................................................................................... 50 ? table 45: the ip0 register ......................................................................................................................... 51 ? table 46: the wdtrel register ............................................................................................................... 51 ? table 47: direction registers and in ternal resources for dio pin groups ............................................... 52 ? table 48: udir control bit ......................................................................................................................... 52 ? table 49: selectable controls using the uxis bits ..................................................................................... 52 ? table 50: the usrintctl1 register ............................................................................................................ 53 ? table 51: the usrintctl2 register ............................................................................................................ 53 ? table 52: the usrintctl3 register ............................................................................................................ 53 ? table 53: the usrintctl4 register ............................................................................................................ 53 ? table 54: the rtcctl register ................................................................................................................... 55 ? table 55: the 32-bit rtc counter .............................................................................................................. 56 ? table 56: the 24-bit rtc accumulator ...................................................................................................... 56 ? table 57: the 24-bit rtc trim (sign magnitude value) ............................................................................. 56 ? downloaded from: http:///
73s1217f data sheet ds_1217f_002 table 58: the int5ctl register .................................................................................................................. 56 ? table 59: the acomp register ................................................................................................................. 57 ? table 60: the int6ctl register .................................................................................................................. 58 ? table 61: the ledctl register ................................................................................................................... 59 ? table 62: the dar register ....................................................................................................................... 63 ? table 63: the wdr register ...................................................................................................................... 63 ? table 64: the swdr register ................................................................................................................... 64 ? table 65: the rdr register ....................................................................................................................... 64 ? table 66: the srdr register .................................................................................................................... 65 ? table 67: the csr register ....................................................................................................................... 65 ? table 68: the int6ctl register .................................................................................................................. 66 ? table 69: the kcol register ..................................................................................................................... 70 ? table 70: the krow register ................................................................................................................... 70 ? table 71: the kscan register .................................................................................................................. 71 ? table 72: the kstat register ................................................................................................................... 72 ? table 73: the ksize register .................................................................................................................... 73 ? table 74: the korderl register ............................................................................................................. 73 ? table 75: the korderh register ............................................................................................................ 74 ? table 76: the int5ctl register .................................................................................................................. 74 ? table 77: the misctl1 register .................................................................................................................. 76 ? table 78: the ckcon register ................................................................................................................. 77 ? table 79: the scsel register .................................................................................................................... 89 ? table 80: the scint register ..................................................................................................................... 90 ? table 81: the scie register ...................................................................................................................... 91 ? table 82: the vccctl register .................................................................................................................... 92 ? table 83: the vcctmr register .................................................................................................................. 93 ? table 84: the crdctl register .................................................................................................................. 94 ? table 85: the stxctl register ................................................................................................................... 95 ? table 86: the stxdata register ................................................................................................................ 96 ? table 87: the srxctl register ................................................................................................................... 97 ? table 88: the srxdata register ............................................................................................................... 98 ? table 89: the scctl register ..................................................................................................................... 99 ? table 90: the scectl register ................................................................................................................. 100 ? table 91: the scdir register ................................................................................................................. 101 ? table 92: the sprtcol register ................................................................................................................. 102 ? table 93: the scclk register ................................................................................................................ 103 ? table 94: the sceclk register .............................................................................................................. 103 ? table 95: the sparctl register ................................................................................................................ 104 ? table 96: the sbytectl register .............................................................................................................. 105 ? table 97: the fdreg register ................................................................................................................. 106 ? table 98: divider ratios provided by the etu counter ........................................................................... 106 ? table 99: divider values for the etu clock ............................................................................................. 107 ? table 100: the crcmsb register ........................................................................................................... 108 ? table 101: the crclsb register ............................................................................................................ 108 ? table 102: the bgt register ................................................................................................................... 109 ? table 103: the egt register ................................................................................................................... 109 ? table 104: the bwtb0 register .............................................................................................................. 110 ? table 105: the bwtb1 register .............................................................................................................. 110 ? table 106: the bwtb2 register .............................................................................................................. 110 ? table 107: the bwtb3 register .............................................................................................................. 110 ? table 108: the cwtb0 register .............................................................................................................. 110 ? table 109: the cwtb1 register .............................................................................................................. 110 ? table 110: the atrlsb register ............................................................................................................. 111 ? table 111: the atrmsb register ............................................................................................................ 111 ? table 112: the ststo register .............................................................................................................. 111 ? table 113: the rlength register ............................................................................................................. 111 ? table 114: smart card sfr table ........................................................................................................... 112 ? table 115: the vddfctl register ............................................................................................................ 113 ? table 116: order numbers and packaging marks ................................................................................... 137 ? 6 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 7 d+ smart card iso interface sclk sio external smart card interface power regulation and vcc control logic gnd vdd tbus1 tbus2 tbus3 tbus0 rxtx erst isbr tclk txd rxd ice interface sec smart card logic iso uart and clock generator flash/rom program memory 64kb data xram 2kb core serial int2 int3 gnd gnd peripheral interface and sfr logic flash interface test ocdsi isr watch- dog timer pmu ports timer_0_ 1 memory_ control control unit ram_ sfr_ control alu d- reset voltage reference and fuse trim circuitry vpd regulator usb i/o and logic ana_in pll and timebases vdd scratch iram 256b 12mhz oscillator x12out x12in col4 col3 col2 col1 col0 row5 row4 row3 row2 row1 row0 keypad interface i 2 c master int. sda scl usr(8:0) drivers usr7 usr6 usr5 usr4 usr3 usr1 usr2 usr0 32khz oscillator x32out x32in rtc vcc rst clk i/o aux2 aux1 pres vpc gnd vbus vp vbat vdd lin off_req on_off gnd led driver led0 figure 1: ic functional block diagram downloaded from: http:///
73s1217f data sheet ds_1217f_002 1 hardware description 1.1 pin description table 1: 73s1217 pinout description pin name pin (68 qfn) type equivalent circuit* description x12in 10 i figure 29 mpu/usb clock crystal oscillator input pin. a 12mhz crystal is required for usb operation. a 1m ? resistor is required between pins x12in and x12out. x12out 11 o figure 29 mpu/usb clock crystal oscillator output pin. x32in 8 i figure 30 rtc clock crystal oscillator input pin. a 32768hz crystal is required for low-power rtc operation. x32out 7 o figure 30 rtc clock crystal oscillator output pin. dp 26 io figure 45 usb d+ io pin, requires series 24 ? resistor. dm 27 io figure 45 usb d- io pin, requires series 24 ? resistor. row(5:0) 0 1 2 3 4 5 21 22 24 33 36 37 i figure 37 keypad row input sense. col(4:0) 0 1 2 3 4 12 13 14 16 19 o figure 38 keypad column output scan pins. usr(7:0) 0 1 2 3 4 5 6 7 35 34 32 31 30 29 23 20 io figure 33 general-purpose user pins, i ndividually configurable as inputs or outputs or as external input interrupt ports. scl 5 o figure 32 i 2 c (master mode) compatible clock signal. note: the pin is configured as an open drain output. when the i2c interface is being used, an external pull up resistor is required. a value of 3k is recommended. sda 6 io figure 31 i 2 c (master mode) compatible data i/o. note: this pin is bi-directional. when the pin is configured as output, it is an open drain output. when the i2c interface is being used, an external pull up resistor is required. a value of 3k is recommended. rxd 17 i figure 35 serial uart receive data pin. txd 18 o figure 32 serial uart transmit data pin. 8 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 9 pin name pin (68 qfn) type equivalent circuit* description int3 48 i figure 35 general purpose interrupt input. int2 49 i figure 35 general purpose interrupt input. sio 47 io figure 31 io data signal for use with external smart card interface circuit such as 73s73s8010x. sclk 45 o figure 32 clock signal for use with external smart card interface circuit. pres 53 i figure 44 smart card presence. active hi gh. note: the pin has a very weak pull down resistor. in noisy environments, an external pull down may be desired to insure against a false card event. clk 55 o figure 42 smart card clock signal. rst 57 o figure 42 smart card reset signal. io 61 io figure 43 smart card data io signal. aux1 60 io figure 43 auxiliary smart card io signal (c4). aux2 59 io figure 43 auxiliary smart card io signal (c8). vcc 58 pso smart card vcc supply voltage output. a 0.47 f capacitor is required and should be located at the smart card connector. the capacitor should be a ceramic type with low esr. gnd 56 gnd smart card ground. vpc 65 psi power supply source for main voltage converter circuit. a 10 f and a 0.1 f capacitor are required at the vpc input. the 10 f capacitor should be a ceramic type with low esr. vbus 62 psi alternate power source input from usb connector or hub. vbat 64 psi alternate power source i nput, typically from two series cells, v > 4v. vp 54 pso intermediate output of main converter circuit. requires an external 4.7 f low esr filter capacitor to gnd. lin 66 psi connection to 10 h inductor for internal step up converter. note: inductor must be rated for 400 ma maximum peak current. on_off 63 i figure 46 power control pin. connected to normally open spst switch to ground. closing switch for duration greater than de- bounce period will turn 73s1217f on. if 73s1217f is on, closing switch will flag the 73s1217f to go to the off state. firmware will control when the power is shut down. downloaded from: http:///
73s1217f data sheet ds_1217f_002 pin name pin (68 qfn) type equivalent circuit* description off_req 52 o figure 36 digital output. if on_off switch is closed (to ground) for de-bounce duration and circuit is on, off_req will go high (request to turn off). this output should be connected to an interrupt pin to signal the cpu core that a request to shut down power has been initiated. the firmware can then perform all of its shut down housekeeping duties before shutting down v dd . tbus(3:0)0 1 2 3 50 46 44 41 io trace bus signals for ice. rxtx 43 io ice control. erst 38 io ice control. isbr 3 io ice control. tclk 39 i ice control. ana_in 15 ai figure 41 analog input pin. this signal goes to a programmable comparator and is used to sense the value of an external voltage. led0 4 io figure 39 special output driver, progra mmable pull-down current to drive led. may also be used as an input. sec 2 i figure 40 input pin for use in programming security fuse. it should be connected to ground when not in use. test 51 di figure 40 test pin, should be connected to ground. vdd 68 28 40 pso v dd supply output pin. a 0.1 f capacitor is recommended at each vdd pin. gnd 9 25 42 67 gnd general ground supply pins for all io and logic circuits. reset 1 i figure 35 reset input, positive assertion. resets logic and registers to default condition. note: to insure proper reset operation after v dd is turned on by application of v bus power or activation of the on/off switch, external reset circuitry must generate a proper reset signal to the 73s1217f. this can be accomplished via a simple rc network. * see the figures in the equivalent circuits section. 10 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 11 1.2 hardware overview the 73s1217f single smart card controller integrates all primary functional blocks required to implement a smart card reader with host serial and / or usb interface. included on chip are an 8051-compatible microprocessor (mpu) which executes up to one instru ction per clock cycle (80515), a fully integrated is0 7816 compliant smart card interface, expansion smar t card interface, full speed usb 2.0 compatible interface, serial interface, i2c interface, 6 x 5 ke ypad interface, ram, flash memory, a real time clock (rtc), and a variety of i/o pins. advanced power management features include a dc-dc converter and on-chip regulators that generate all the necessary voltages for the circuit: primarily a smart card supply vcc, (selectable to 1.8v, 3v or 5v) and a 3.3v digital voltage output (vdd, pin #68) t hat must be connected to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (thes e are not internally connected). should external circuitry require a 3.3v digital power supply, t he vdd output is capable of supplying additional current. the whole ic can be powered up either from a usb bus-power supply (vbus +5 v typical), or from a typical set of battery cells vbat. automated switch ing between these supply inputs give the priority to vbus to save the battery life. a functional block diagram of the 73s1217f is shown in figure 1 . 1.3 80515 mpu core 1.3.1 80515 overview the 73s1217f includes an 80515 mpu (8-bit, 8051-compatible) that performs most instructions in one clock cycle. the 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. normally a machine cycl e is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. this leads to an 8x performance (average) improvement (in terms of mips) over the in tel 8051 device running at the same clock frequency. actual processor clocking speed can be adjusted to the total processing demand of the application (cryptographic calculations, key management, me mory management, and i/o management) using the xram special function register mpuckctl . typical smart card, usb, serial, keyboard, i2c and rtc management functions are available for the mpu as part of the teridian standard library. a standard ansi c 80515-application programming interface library is available to hel p reduce design cycle. refer to the 73s12xxf software users guide . 1.3.2 memory organization the 80515 mpu core incorporates the harvard ar chitecture with separate code and data spaces. memory organization in the 80515 is similar to that of the industry standard 8051. there are three memory areas: program memory (flash), external data memory (xram), and internal data memory (iram). data bus address space is a llocated to on-chip memory as shown table 2 . table 2: mpu data memory map address (hex) memory technology memory type typical usage memory size (bytes) 0000-ffff flash memory non-volatile program and non-volatile data 64kb 0000-07ff static ram volatile mpu data xram 2kb fc00-ffff external sfr volatile peripheral control 1kb note: the iram is part of the core and is addressed differently. downloaded from: http:///
73s1217f data sheet ds_1217f_002 program memory: the 80515 can address up to 64kb of program memory space from 0x0000 to 0xffff. program memory is read when the mpu fetches instructions or performs a movc operation. after reset, the mpu starts program execution from location 0x0000. the lower part of the program memory includes reset and interrupt vectors. the interr upt vectors are spaced at 8- byte intervals, starting from 0x0003. reset is located at 0x0000. flash memory: the program memory consists of flash memory. the flash memory is intended to primarily contain mpu program code. flash erasure is initiated by wr iting a specific data pattern to specific sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the flash memory. the mass erase sequence is: 1. write 1 to the flsh_meen bit in the flshctl register (sfr address 0xb2[1]). 2. write pattern 0xaa to erase (sfr address 0x94) note: the mass erase cycle can only be initiated when the ice port is enabled. the page erase sequence is: 1. write the page address to pgaddr (sfr address 0xb7[7:1]) 2. write pattern 0x55 to erase (sfr address 0x94) the pgaddr register denotes the page address for page erase. the page size is 512 (200h) bytes and there are 128 pages within the flash memory. the pgaddr denotes the upper seven bits of the flash memory address such that bit 7:1 of the pgaddr corresponds to bit 15:9 of the flash memory address. bit 0 of the pgaddr is not used and is ignored. the mp u may write to the flash memory. this is one of the non-volatile storage options available to the user. the flshctl sfr bit flsh_pwe (flash program write enable) differentiates 80515 data store instructions (movx@dptr,a) between flash and xram writes. before setting flsh_pwe, all interr upts need to be disabled by setting eal = 1. table 3 shows the location and description of the 73s1217f flash-specific sfrs. any flash modifications must set the cpuclk to operate at 3.6923 mhz ( mpuclkctl = 0x0c) before any flash memory operations are executed to insure the proper timing when modifying the flash memory. 12 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 13 table 3: flash special function registers register sfr address r/w description erase 0x94 w this register is used to initiate either the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for erase in order to initiate the appropriate erase cycle (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to pgaddr @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug port must be enabled. any other pattern written to erase will have no effect. pgaddr 0xb7 r/w flash page erase address register containing the flash memory page address (page 0 through 127) that will be erased during the page erase cycle (default = 0x00). note: the page address is shifted left by one bit (see detailed description above). must be re-written for each new page erase cycle. flshctl 0xb2 r/w bit 0 (flsh_pwe): program write enable: 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space (flash) @ dptr. this bit is automatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. w bit 1 (flsh_meen): mass erase enable: 0 C mass erase disabled (default). 1 C mass erase enabled. must be re-written for each new mass erase cycle. r/w bit 6 (secure): enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. internal data memory: the internal data memory provides 256 bytes (0x00 to 0xff) of data memory. the internal data memory address is always one by te wide and can be accessed by either direct or indirect addressing. the special function registers occupy the upper 128 bytes . this sfr area is available only by direct addressing. indir ect addressing accesses the upper 128 bytes of internal ram. the lower 128 bytes contain working registers and bi t-addressable memory. the lower 32 bytes form four banks of eight registers (r0-r7). two bits on the program memory status word ( psw ) select which bank is in use. the next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00- 0x7f. all of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. table 4 shows the internal data memory map. downloaded from: http:///
73s1217f data sheet ds_1217f_002 table 4: internal data memory map address direct addressing indirect addressing 0xff special function registers (sfrs) ram 0x80 0x7f byte-addressable area 0x30 0x2f byte or bit-addressable area 0x20 0x1f register banks r0r7 (x4) 0x00 external data memory: while the 80515 can address up to 64kb of external data memory in the space from 0x0000 to 0xffff, only the memory ranges shown in figure 2 contain physical memory. the 80515 writes into external data memory when t he mpu executes a movx @ri,a or movx @dptr,a instruction. the mpu reads external data memo ry by executing a movx a,@ri or movx a,@dptr instruction. there are two types of instructions, differing in whet her they provide an eight-bit or sixteen-bit indirect address to the external data ram. in the first type (movx a,@ri), the contents of r0 or r1, in the current register bank, provide the eight lower-ordered bits of address. this method allows t he user access to the first 256 bytes of the 2kb of external data ram. in the second type of mo vx instruction (movx a,@dptr), the data pointer generates a sixteen-bit address. 14 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 15 address use address use 0xffff flash program memory 64k bytes 0xffff peripheral control registers (128b) 0xff80 0xff7f smart card control (384b) 0xfe00 0xfdff usb registers (512b) 0xfc00 0xfbff C 0x0800 address use 0x07ff xram indirect access direct access 0xff byte ram sfrs 0x80 0x7f byte ram 0x48 0x47 bit/byte ram 0x20 0x1f register bank 3 0x18 0x17 register bank 2 0x10 0x0f register bank 1 0x08 0x07 register bank 0 0x0000 0x0000 0x00 program memory external data memory internal data memory figure 2: memory map dual data pointer: the dual data pointer accelerates the block moves of data. the standard dptr is a 16-bit register that is used to address external me mory. in the 80515 core, the standard data pointer is called dptr, the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data pointer select bit is located at the lsb of the dps iram special function register (dps.0). dptr is selected when dps.0 = 0 and dptr1 is selected when dps.0 = 1. the user switches between pointers by toggling t he lsb of the dps register. all dptr-related instructions use the currently selected dptr for any activity. note: the second data pointer may not be supported by certain compilers. downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.4 program security two levels of program and data security are available. each level requires a specific fuse to be blown in order to enable or set the specific security mode. mode 0 security is enabled by setting the secure bit (bit 6 of sfr register flshctl 0xb2). mode 0 limits the ice interface to only allow bulk erase of the flash program memory. all other ic e operations are blocked. this guarantees the security of the users mpu program code. security (mode 0) is enabled by mpu code that sets the secure bit. the mpu code must execute the setting of the secure bit imm ediately after a reset to properly enable mode 0. this should be the first instruction after the reset vector jump has been executed. if the startup.a51 assembly file is used in an application, then it mu st be modified to set the secure bit after the reset vector jump. if not using startup.a51 , then this should be the first instruction in main(). once security mode 0 is enabled, the only way to disable it is to per form a global erase of the flash followed by a full circuit reset. once the flash has been erased and the reset has been executed, security mode 0 is disabled and the ice has full control of the core. the flash can be reprogrammed after the bulk erase operation is completed. global erase of the flash will also clear the data xram memory. the security enable bit (secure) is reset whenever the mpu is reset. hardware associated with the bit only allows it to be set. as a result, the code may set the secure bit to enable the security mode 0 feature but may not reset it. once the secure bit is set, the code is protected and no external read of program code in flash or data (in xram) is possible. in order to invoke the security mode 0, the secset0 (bit 1 of xram sfr register secreg 0xffd7) fuse must be blown beforehand or the security mode 0 will not be enabled. the secset0 and secset1 fuses once blown, cannot be overridden. specifically, when secure is set: ? the ice is limited to bulk flash erase only. ? page zero of flash memory may not be page-erased by either mpu or ice. page zero may only be erased with global flash erase. note that global flash erase erases xram whether the secure bit is set or not. ? writes to page zero, whether by mpu or ice, are inhibited. security mode 1 is in effect when the secset1 fu se has been programmed (blown open). in security mode 1, the ice is completely and permanently dis abled. the flash program memory and the mpu are not available for alteration, observation, nor control. as soon as the fuse has been blown, the ice is disabled. the testing of the secset1 fuse will o ccur during the reset and before the start of pre-boot and boot cycles. this mode is not reversible, nor reco verable. in order to blow the secset1 fuse, the sec pin must be held high for the fuse burning sequence to be executed properly. the firmware can check to see if this pin is held high by readi ng the secpin bit (bit 5 of xram sfr register secreg 0xffd7). if this bit is set and the firmware desires , it can blow the secset1 fuse. the burning of the secset0 does not require the sec pin to be held high. in order to blow the fuse for secset1 and secset0, a parti cular set of register writ es in a specific order need to be followed. there are two additional registers that need to have a specific value written to them in order for the desired fuse to be blown. these registers are fusectl (0xffd2) and trimpctl (0xffd1). the sequence for blow ing the fuse is as follows: 1. write 0x54h to fusectl . 2. write 0x81h for security mode 0 note: only program one security mode at a time. 3. write 0x82h for security mode 1 note: sec pin must be high for security mode 1. 4. write 0xa6 to trimpctl . 5. delay about 500 us 6. write 0x00 to trimpctl and fusectl . 16 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 17 table 5: program security registers register sfr address r/w description flshctl 0xb2 r/w bit 0 (flsh_pwe): program write enable: 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space (flash) @ dptr. this bit is automatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. w bit 1 (flsh_meen): mass erase enable: 0 C mass erase disabled (default). 1 C mass erase enabled. must be re-written for each new mass erase cycle. r/w bit 6 (secure): enables security provisions that prev ent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. trimpctl 0xffd1 w 0xa6 value will cause the sele cted fuse to be blown. all other values will stop the burning process. fusectl 0xffd2 w 0x54 value will set up for securi ty fuse control. all other values are reserved and should not be used. secreg 0xffd7 w bit 7 (paramsec): 0 C normal operation. 1 C enable permanent programming of the security fuses. r bit 5 (secpin): indicates the state of the sec pin. the sec pin is held low by a pull-down resistor. the user can force this pin high during boot sequence time to indicate to firmware that sec mode 1 is desired. r/w bit 1 (secset1): see the program security section. r/w bit 0 (secset0): see the program security section. downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.5 special function registers (sfrs) the 1217 utilizes numerous sfrs to communicate with the many 1217 peripherals. this results in the need for more sfr locations outside the direct address iram space (0x80 to 0xff). while some peripherals are mapped to unused iram sfr locations , additional sfrs for the usb, smart card and other peripheral functions are mapped to the t op of the xram data space (0xfc00 to 0xffff). 1.5.1 internal data special function registers (sfrs) the special function registers map is shown in table 6. table 6: iram special function registers locations hex\bin x000 x001 x010 x011 x100 x101 x110 x111 bin/ hex f8 ff f0 b f7 e8 ef e0 a e7 d8 brcon df d0 psw kcol krow kscan kstat ksize korderl korderh d7 c8 t2con cf c0 ircon c7 b8 ien1 ip1 s0relh s1relh bf b0 flshctl pgaddr b7 a8 ien0 ip0 s0rell af a0 a7 98 s0con s0buf ien2 s1con s1buf s1rell 9f 90 usr70 udir70 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 mclkctl 8f 80 sp dpl dph dpl1 dph1 wdtrel pcon 87 only a few addresses are used, the others are not implemented. sfrs specific to the 73s1217f are shown in bold print (gray background). any read access to unimplemented addresses will return undefined data, while most write access will have no effect. however, a few locations are reserved and not user configurable in the 73s1217f. writes to the unused sfr locations can affect the operation of the core and therefore must not be written to. this applies to all the sfr areas in both the iram and xram spaces. in addition, all unused bit locations within valid sfr registers must be left in their default (power on default) states. 18 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 19 1.5.2 iram special function registers (generic 80515 sfrs) table 7 shows the location of the sfrs and the value they assume at reset or power-up. table 7: iram special function registers reset values name location reset value description sp 0x81 0x07 stack pointer dpl 0x82 0x00 data pointer low 0 dph 0x83 0x00 data pointer high 0 dpl1 0x84 0x00 data pointer low 1 dph1 0x85 0x00 data pointer high 1 wdtrel 0x86 0x00 watchdog timer reload register pcon 0x87 0x00 power control tcon 0x88 0x00 timer/counter control tmod 0x89 0x00 timer mode control tl0 0x8a 0x00 timer 0, low byte tl1 0x8b 0x00 timer 1, high byte th0 0x8c 0x00 timer 0, low byte th1 0x8d 0x00 timer 1, high byte mclkctl 0x8f 0x0a master clock control usr70 0x90 0xff user port data (7:0) udir70 0x91 0xff user port direction (7:0) dps 0x92 0x00 data pointer select register erase 0x94 0x00 flash erase s0con 0x98 0x00 serial port 0, control register s0buf 0x99 0x00 serial port 0, data buffer ien2 0x9a 0x00 interrupt enable register 2 s1con 0x9b 0x00 serial port 1, control register s1buf 0x9c 0x00 serial port 1, data buffer s1rell 0x9d 0x00 serial port 1, reload register, low byte ien0 0xa8 0x00 interrupt enable register 0 ip0 0xa9 0x00 interrupt priority register 0 s0rell 0xaa 0xd9 serial port 0, reload register, low byte flshctl 0xb2 0x00 flash control pgaddr 0xb7 0x00 flash page address ien1 0xb8 0x00 interrupt enable register 1 ip1 0xb9 0x00 interrupt priority register 1 s0relh 0xba 0x03 serial port 0, reload register, high byte s1relh 0xbb 0x03 serial port 1, reload register, high byte ircon 0xc0 0x00 interrupt request control register t2con 0xc8 0x00 timer 2 control psw 0xd0 0x00 program status word kcol 0xd1 0x1f keypad column downloaded from: http:///
73s1217f data sheet ds_1217f_002 20 rev. 1.2 name location reset value description krow 0xd2 0x3f keypad row kscan 0xd3 0x00 keypad scan time kstat 0xd4 0x00 keypad control/status ksize 0xd5 0x00 keypad size korderl 0xd6 0x00 keypad column ls scan order korderh 0xd7 0x00 keypad column ms scan order brcon 0xd8 0x00 baud rate control register (only brcon.7 bit used) a 0xe0 0x00 accumulator b 0xf0 0x00 b register 1.5.3 external data special function registers (sfrs) a map of the xram special function registers is show n in table 8. the smart card registers are listed separately in table 114 . table 8: xram special function registers reset values name location reset value description dar 0x ff80 0x00 device address register (i 2 c) wdr 0x ff81 0x00 write data register (i 2 c) swdr 0x ff82 0x00 secondary write data register (i 2 c) rdr 0x ff83 0x00 read data register (i 2 c) srdr 0x ff84 0x00 secondary read data register (i 2 c) csr 0x ff85 0x00 control and status register (i 2 c) usrintctl1 0x ff90 0x00 external interrupt control 1 usrintctl2 0x ff91 0x00 external interrupt control 2 usrintctl3 0x ff92 0x00 external interrupt control 3 usrintctl4 0x ff93 0x00 external interrupt control 4 int5ctl 0x ff94 0x00 external interrupt control 5 int6ctl 0x ff95 0x00 external interrupt control 6 mpuckctl 0x ffa1 0x0c mpu clock control rtcctl 0x ffb0 0x00 real time clock control rtccnt3 0x ffb1 0x00 rtc count 3 rtccnt2 0x ffb2 0x00 rtc count 2 rtccnt1 0x ffb3 0x00 rtc count 1 rtccnt0 0x ffb4 0x00 rtc count 0 rtcacc2 0x ffb5 0x00 rtc accumulator 2 rtcacc1 0x ffb6 0x00 rtc accumulator 1 rtcacc0 0x ffb7 0x00 rtc accumulator 0 rtctrim2 0x ffb8 0x00 rtc trim 2 rtctrim1 0x ffb9 0x00 rtc trim 1 rtctrim0 0x ffba 0x00 rtc trim 0 acomp 0x ffd0 0x00 analog compare register trimpctl 0x ffd1 0x00 trim pulse control downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 21 name location reset value description fusectl 0x ffd2 0x00 fuse control vddfctl 0x ffd4 0x00 vddfault control secreg 0x ffd7 0x00 security register misctl0 0x fff1 0x00 miscellaneous control register 0 misctl1 0x fff2 0x10 miscellaneous control register 1 ledctl 0x fff3 0xff led control register accumulator (acc, a): acc is the accumulator register. most instructions use the accumulator to hold the operand. the mnemonics for accumulator-specific inst ructions refer to accumulator as a, not acc. b register: the b register is used during multiply and di vide instructions. it can also be used as a scratch-pad register to hold temporary data. downloaded from: http:///
73s1217f data sheet ds_1217f_002 program status word (psw): table 9: psw register flags msb lsb cv ac f0 rs1 rs ov C p bit symbol function psw.7 cv carry flag. psw.6 ac auxiliary carry flag for bcd operations. psw.5 f0 general purpose flag 0 available for user. psw.4 rs1 register bank select control bi ts. the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 (0x00 C 0x07) 01 bank 1 (0x08 C 0x0f) 10 bank 2 (0x10 C 0x17) 11 bank 3 (0x18 C 0x1f) psw.3 rs0 psw.2 ov overflow flag. psw.1 f1 general purpose flag 1 available for user. psw.0 p parity flag, affected by hardwar e to indicate odd / even number of one bits in the accumulator, i.e. even parity. stack pointer (sp): the stack pointer is a 1-byte register init ialized to 0x07 after reset. this register is incremented before push and call instructions, c ausing the stack to begin at location 0x08. data pointer: the data pointer (dptr) is 2 bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2-byte register (mov dptr,#dat a16) or as two registers (e.g. mov dpl,#data8). it is generally used to access external code or dat a space (e.g. movc a,@a+dptr or movx a,@dptr respectively). program counter: the program counter (pc) is 2 bytes wi de initialized to 0x0000 after reset. this register is incremented during the fetching operation code or when operating on data from program memory. note: the program counter is not mapped to the sfr area. port registers: the i/o ports are controlled by special function register usr70 . the contents of the sfr can be observed on corresponding pins on the ch ip. writing a 1 to any of the ports (see table 10 ) causes the corresponding pin to be at high level (3.3 v), and writing a 0 causes the corresponding pin to be held at low level (gnd). the data direction register udir70 define individual pins as input or output pins (see the user (usr) ports section for details). table 10: port registers register sfr address r/w description usr70 0x90 r/w register for user port bits 7:0 read and write operations (pins usr0 usr7). udir70 0x91 r/w data direction register for user port bits 0:7. setting a bit to 0 means that the corresponding pin is an output. all ports on the chip are bi-directional. each cons ists of a latch (sfr usr70), an output driver, and an input buffer, therefore the mpu can output or read data through any of thes e ports if they are not used for alternate purposes. 22 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 23 1.6 instruction set all instructions of the generic 8051 microcontroller are supported. a complete list of the instruction set and of the associated op-codes is contained in the 73s12xxf software users guide . and of the associated op-codes is contained in the 73s12xxf software users guide . 1.7 peripheral descriptions 1.7 peripheral descriptions 1.7.1 oscillator and clock generation 1.7.1 oscillator and clock generation the 73s1217f has two oscillator circuits; one for t he main cpu clock and another for the rtc. the main oscillator circuit is designed to operate with va rious crystal or external clock frequencies. an internal divider working in conjunction with a pll and vco provides a 96mhz internal clock within the 73s1217f. 96 mhz is the required frequency for proper oper ation of specific peripheral blocks such as the usb, specific timers, iso 7816 uart and interf aces, step-up converter, and keypad. the clock generation and control circuits are shown in figure 3 . the 73s1217f has two oscillator circuits; one for t he main cpu clock and another for the rtc. the main oscillator circuit is designed to operate with va rious crystal or external clock frequencies. an internal divider working in conjunction with a pll and vco provides a 96mhz internal clock within the 73s1217f. 96 mhz is the required frequency for proper oper ation of specific peripheral blocks such as the usb, specific timers, iso 7816 uart and interf aces, step-up converter, and keypad. the clock generation and control circuits are shown in figure 3 . low xtal osc vco phase freq det cpu clock divider 6 bits mclk 96mhz lmclk=32765hz 1.5-48mhz mpu clock - cpclk smart card logic block clock scclk sclk clock prescaler 6bits sc/sce clock prescaler 6bits sel etu clock divider 12 bits div 2 cpuckdiv see sc clock descriptions for more accurate diagram etuclk mcount(2:0) keyclk lclk=32768hz x32in x32out i2cclk 1khz 400khz usbclk 48mhz divide by 120 divider /2930 high xtal osc x12in x12out m divider /(2*n + 4) hclk hoscen 12.00mhz 32768hz 12.00mhz usbckenb div 2 iclk 32koscenb scckenb selsc divide by 96 clk1m 1mhz 7.386mhz 7.386mhz 3.6923mhz div 32 i2c_2x 800khz div 2 sceclk div 2 div 2 mux rtcclk figure 3: clock generation and control circuits downloaded from: http:///
73s1217f data sheet ds_1217f_002 the master clock control register enables different se ctions of the clock circuitry and specifies the value of the vco mcount divider. the mclk must be configured to operate at 96mhz to ensure proper operation of some of the peripheral blo cks according to the following formula: mclk = (mcount * 2 + 4) * f xtal = 96mhz mcount is configured in the mclkctl register must be bound between a value of 1 to 7. the possible crystal or external clock frequencies fo r getting mclk = 96mhz are shown in table 11 . table 11: frequencies and mcount values for mclk = 96mhz f xtal (mhz) mcount (n) 12.00 2 9.60 3 8.00 4 6.86 5 6.00 6 master clock control register (mclkctl): 0x8f ? 0x0a table 12: the mclkctl register msb lsb hsoen kben scen usben 32ken mct.2 mct.1 mct.0 bit symbol function mclkctl.7 hsoen high-speed oscillator disable. when set = 1, disables the high-speed crystal oscillator and vco/pll system. do not set this bit = 1. mclkctl.6 kben 1 = disable the keypad logic clock. mclkctl.5 scen 1 = disable t he smart card logic clock. mclkctl.4 usben 1 = disable the usb logic clock. mclkctl.3 32ken 1 = disable the 32khz oscillator. when the 32khz oscillator is enabled, the rtc and other circuits such as debounce clocks are clocked using the 32khz oscillator output. when disabled, the main oscillator provides the 32khz clock for the rtc and other circuits. note: this bit must be set if there is no 32khz crystal. some internal clocks and circuits will not run if the oscillator is enabled and no crystal is connected. mclkctl.2 mct.2 this value determines the ratio of the vco frequency (mclk) to the high-speed crystal oscillator frequency such that: mclk = (mcount*2 + 4)* f xtal . the default value is mcount = 2h such that mclk = (2*2 + 4)*12.00mhz = 96mhz. mclkctl.1 mct.1 mclkctl.0 mct.0 the mpu clock that drives the cp u core defaults to 3.6923mhz after reset. the mpu clock is scalable by configuring the mpu cl ock control register ( mpuckctl ). 24 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 25 mpu clock control register (mpuckctl): 0xffa1 ? 0x0c table 13: the mpuckctl register msb lsb C C mdiv.5 mdiv.4 mdiv.3 mdiv.2 mdiv.1 mdiv.0 bit symbol function mpuckctl.7 C mpuckctl.6 C mpuckctl.5 mdiv.5 this value determines the ratio of the mpu master clock frequency to the vco frequency (mclk) such that mpuclk = mclk/(2 * (mp uckdiv(5:0) + 1)). do not use values of 0 or 1 for mpuckdiv(n). default is 0ch to set cpclk = 3.6923mhz. mpuckctl.4 mdiv.4 mpuckctl.3 mdiv.3 mpuckctl.2 mdiv.2 mpuckctl.1 mdiv.1 mpuckctl.0 mdiv.0 the oscillator circuits are designed to connect directly to standard parallel resonant crystal in a pierce oscillator configuration. each side of the crys tal should include a 22pf capacitor to ground for both oscillator circuits and a 1m ? resistor is required across the 12mhz crystal. the cpu clock is available as an output on pin cpuclk. 73s1217f x12in x12out x32in x32out 12mhz 22pf 22pf 22pf 22pf 32khz 1m note: the crystals should be placed as close as possible to the ic, and vias should be avoided. figure 4: oscillator circuit downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.2 power supply management the detailed power supply management logic block diagram is shown in figure 5. v bus v bat v busth + - q q set clr d debounce circuit on_off dc-dc converter / pass through* delay circuit (por) en vpc vp vp vcc regulator lin off_req int3 mpu int pwrdn* *pwrdn bit in misctl0 vdd vcc power control vcc voltage select vcc enable pass through mode enable pten q q set clr s r nc no *pass through -> vp = vpc smart card power to optional external circuits 20ma max. vdd regulator vdd to internal circuits figure 5: detailed power management logic block diagram the 73s1217f contains a power supply and converter ci rcuit that takes power from any one of three sources; v pc , v b us , or v bat . v pc is specified to range from 2.7 to 6.5 volts. it c an typically be supplied by a single cell battery with a voltage range of 2.7 to approximately 3.1 volts or by a standard supply of 3.3 or 5 volts. 26 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 27 v bus is typically supplied by an external power suppl y and ranges in value from 4.4 to 5.5 volts (6.5v maximum). v bat is expected to be supplied from a battery of three to four series connected cells with a voltage value of 4.0 to 6.5 volts. v bat and v bus are internally switched to v pc by two separate fet switches configured as a spdt switch (break-before-make). they will not be enabled at the same time. v bus is automatically selected in lieu of v bat when v bus is present (i.e. v bus always has the priority). if v pc is provided and either v bat or v bus is also used, the source of v pc must be diode isolated from the v pc pin to prevent current flow from v bat or v bus into the v pc source. the power that is supplied to the v pc pin (externally or internally, i.e. through v bat or v bus C see above) is up-converted to the intermediate voltage v p utilizing an inductive, step-up converter. a series power inductor (nominal value = 10 h) must be connected from v pc to the pin lin, and a 10 f low esr filter capacitor must be connected to v pc . v p requires a 4.7 f filter capacitor and will have a nominal value of 5.5v during normal operation. v p is used internally by the smart card electrical interf ace circuit and is regulated to the desired smart card supply v cc voltage (can be programmed for values of 5v, 3v, or 1.8v). v p is also used internally to generate a 3.3v nominal, regulated power supply v dd . v dd is output on pin 68 and must be directly tied to all other v dd pins on the 73s1217f (pins 28 and 40). v dd powers all the digital logic, input/output buffering, and analog functions. it can also be used for external circuitry: up to 20ma current can be supplied to external devices simultaneously to the 73s1217fs digital core maximum consumption. 1.7.3 power on/off the 73s1217f features an on_off input pin for a mo mentary contract, main -system on/off switch. the purpose of this switch is to place the circuit in a very low-power mode C the off mode C where the digital core of the circuit is no longer powered, therefore allowing the lowest possible current consumption. when in off mode, an action on the on/off switch w ill turn-on the power supply of the digital core (v dd ) and apply a power-on-reset condition. alternativel y, entering the off mode from the on mode requires firmware action. when in on mode, an action on the on/off switch w ill send a request to the controller that will have to be acknowledged (firmware action required) in order to enter the off state. when placed into the off state, the 73s 1217f will consume minimum current from v pc and v bat ; v p and v dd will be unavailable (v dd out = 0v and v p = 0v). when in on mode, the 73s1217f will operate normally, with all the features described in this document available. v p and v dd will be available (v dd out = 3.3v and v p = 5.5v nominal). whenever v bus power is supplied, the circuit will be automatica lly in the on state: the functions of the on/off switch and circuitry are overridden and t he 73s1217f is in the on state with v p and v dd available. without v bus applied, the circuit is by default in the off state, and will respond only to the on_off pin. the on_off pin should be connected to an spst switch to ground. if the circuit is off and the switch is closed for a de-bounce period of 50-100ms, the circuit will go into the on state wherein all functions are operating in normal fashion. if the circuit is in the on state and the on_off pin is connected to ground for a period greater than the de-bounce per iod, off_req will be asserted high and held regardless of the state of on/off. the off_re q signal should be connected to one of the interrupt pins to signal the cpu core that a request to shutdown has been initiated. the firmware will downloaded from: http:///
73s1217f data sheet ds_1217f_002 acknowledge this request by setting t he scpwrdn bit in the smart card v cc control/status register ( vccctl ) high after it has completed all shutdown activi ties. when scpwrdn is set high, the circuit will deactivate the smart card interface if required and turn off all analog functions and the v dd supply for the logic and companion circuits. the default state upon application of power is the off state unless power is supplied to the v bus supply. note that at any time, the firmware may assert scpwrdn and the 73s1217f will go into the off state (when v bus is not present). if the off switch function is not desired and the application does not need to shut down power on vdd, the on_off input can be permanently grounded which will automatically turn on vdd when power is supplied on any of the vpc, vbat or vbus power supply inputs. if power is applied to both v bat and v bus , the circuit will automatically consume power from only the v bus source. the 73s1217f will be unconditionally on when v bus is applied. if the v bus source is removed, the 73s1217f will switchover to the vbat input supply and remain in the on state. the firmware should assert scpwrdn based on no activity or v bus removal to reduce battery power consumption. when operating from v bus , and not calling for v cc , the step-up converter becomes a simple switch connecting v bus to v p in order to save power. this condi tion is appropriate for the usb suspend state. the usb suspend state requires the power supply current to be less than 500ua. in order to obtain and meet this low current limitation, the firm ware must configure the 73s1217f into a power-down condition using less than 20ua from v dd . note: when the on_off switch function is not needed, i.e. when the 73s1217f must be in an always- on state when using another supply than vbus (v pc or v bat ), some external discrete components are needed. 1.7.4 power control modes the 73s1217f contains circuitry to disable portions of the device and place it into a lower power standby mode or power down the 73s1217f into its off mode. the standby mode will stop the core, clock subsystem and the peripherals connected to it. this is accomplished by either shutting off the power or disabling the clock going to the block. the miscellaneous control registers misctl0 , misctl1 and the master clock control register ( mclkctl ) provide control over the power modes. the pwrdn bit in misctl0 will set up the 73s1217f for either standby or off modes. depending on the state of the on/off circuitry and power applied to the vbus inpu t, the 73s1217f will go into either standby mode or power off mode. if system power is provided by, vbu s or the on/off circuitry is in the on state, the mpu core will placed into standby mode. if t he vbus input is not sourcing power and the on/off circuitry is in the off state, setting the pwrdn bi t will shut down the converter and vp will turn off. this in turn will turn off the vdd supply and t he 73s1217f will be turned off. the power down modes should only be initiated by setting the pwrdn bit in the misctl0 register and not by manipulating individual control bits in various registers. figure 6 shows how the pwrdn bit controls the various functions that comprise power down state 28 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 29 vddfault analog functions (vco, pll, reference and bias circuits, etc.) usb transceiver (suspend mode) 32k osc analog compare high speed osc mclckctl - 32ken misctl1 - usbpen misctl1 - anapen misctl0 - pwrdn vddfctl - vddfen acomp - cmpen mclckctl - hosen smart card power scvccctl - scprdn + + + + + + usb suspend these are the registers and the names of the control bits. these are the block references. pwrdn signal note: the pwrdn signal is not the direct version of the pwrdn bit. there are delays from assertion of the pwrdn bit to the assertion of the pwrdn signal (32 mpu clocks) refer to the power down sequence diagram. pd_analog flash read pulse one-shot circuit misctl1 - frpen + figure 6: power-down control when the pwrdn bit is set, the clock subsystem will pr ovide a delay of 32 mpuclk cycles to allow the program to set the stop bit in the pcon register. this delay will enable the program to properly halt the core before the analog circuits shut down (high s peed oscillator, vco/pll, voltage reference and bias circuitry, etc.). the pdmux bit in sfr int5ctl s hould be set prior to setting the pwrdn bit in order to configure the wake up interrupt logic. the power down mode is de-asserted by any of the interrupts connected to external interrupts 0, 4 and 5 (external usr[0:7], smart card and keypad). these interrupt sources are ored together and routed through delay logic into int0 to provide this functionality. the interrupt will turn on the power to all sections that were shut off and start the clock subsystem. after the clock subsystem clocks start running, the mpuclk begi ns to clock a 512 count delay counter. when the counter times out, the interrupt will then be ac tive on int0 and the program can resume. figure 7 shows the detailed logic for waking up the 73s1217f from a power down state using these specific interrupt sources. figure 8 shows the timing associated with the power down mode. downloaded from: http:///
73s1217f data sheet ds_1217f_002 usr[7:0] control usrxintsrc set to 4(ext int0 high) or 6(ext int0 low) 1 0 int5 int4 resetb tc clr 9 bit cntr resetb ce pdmux (ff94h:bit7) mpu int0 pwrdn_analog q clr d pwrdn (fff1h:bit7) usr0 usr6 usr1 usr2 usr3 usr4 usr5 usr7 tc ce clr 5 bit cntr notes: 1. the counters are clocked by the mpuclk 2. tc - terminal count (high at overflow) 3. ce - count enable resetb figure 7: detail of power-down interrupt logic pwrdn bit pwrdn sig ext. event int0 to mpu mpu stop analog enable pll clocks t1 t2 t3 t4 t5 t6 t0 t7 t0 : mpu sets pwrdn bit t1 : 32 mpu clock cycles after t0, the pwrdn si g is asserted, turning all analog functions off. t2 : mpu executes stop instruction, must be done prior to t1. t3 : analog functions go to off condition . no vref, pll/vco, ibias, etc. text text : an external event (rtc, keypad, card event, usb) occurs. t4 : pwrdn bit and pwrdn signal ar e cleared by external event. t5 : high-speed oscillat or/pll/vco operating. t6 : after 512 mpu clock cycles, int0 to mpu is asserted. t7 : int0 causes mpu to exit stop condition. figure 8: power-down sequencing 30 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 31 external interrupt control register (int5ctl): 0xff94 ? 0x00 table 14: the int5ctl register msb lsb pdmux C rtcien rtcint usbien usbint kpien kpint bit symbol function int5ctl.7 pdmux when set = 1, enables interrupts from usb, rtc, keypad (normally going to int5), smart card interrupts (normally going to int4), or usr(7:0) pins (int0) to cause interrupt on int0. the assertion of the interrupt to int0 is delayed by 512 mpu clocks to allow the analog circui ts, including the clock system, to stabilize. this bit must be set prior to asserting the pwrdn bit in order to properly configure the interrupts that will wake up the circuit. this bit is reset = 0 when this register is read. int5ctl.6 C int5ctl.5 rtcien rtc interrupt enable. int5ctl.4 rtcint rtc interrupt flag. int5ctl.3 usbien usb interrupt enable. int5ctl.2 usbint usb interrupt flag. int5ctl.1 kpien keypad interrupt enable. int5ctl.0 kpint keypad interrupt flag. miscellaneous control register 0 (misctl0): 0xfff1 ? 0x00 table 15: the misctl0 register msb lsb pwrdn C C C C C slpbk ssel bit symbol function misctl0.7 pwrdn this bit sets the circuit into a lo w-power condition. all analog (high speed oscillator and vco/pll) functions are disabled 32 mpu clock cycles after this bit is set = 1. this allows time for the next instruction to set the stop bit in the pcon register to stop the cpu core. t he rtc will stay active if it is set to operate from the 32khz oscillator. the mpu is not operative in this mode. when set, this bit overrides the individual control bits that otherwise control power consumption. misctl0.6 C misctl0.5 C misctl0.4 C misctl0.3 C misctl0.2 C misctl0.1 slpbk uart loop back testing mode. misctl0.0 ssel serial port pins select. downloaded from: http:///
73s1217f data sheet ds_1217f_002 miscellaneous control register 1 (misctl1): 0xfff2 ? 0x10 table 16: the misctl1 register msb lsb C C frpen flsh66 C anapen usbpen usbcon bit symbol function misctl1.7 C misctl1.6 C misctl1.5 frpen flash read pulse enable (low). if fr pen = 1, the flash read signal is passed through with no change. when fr pen = 0 a one-shot circuit that shortens the flash read signal is enabl ed to save power. the flash read pulse will shorten to 40 or 66ns ( approximate based on the setting of the flsh66 bit) in duration, regardless of the mpu clock rate. for mpu clock frequencies greater than 10mhz, this bit should be set high. misctl1.4 flsh66 when high, creates a 66ns flash read pulse, otherwise creates a 40ns read pulse when frpen is set. misctl1.3 C misctl1.2 anapen* 0 = enable the analog functions that generate vref and bias current functions. setting high will turn off the vpd regulator and vco/pll functions. misctl1.1 usbpen 0 = enable the usb differential transceiver. misctl1.0 usbcon usb pull- up resistor connect enable. *note: the anapen bit should never be set under nor mal circumstances. power down control should only be initiated via use of the pwrdn bit in misctl0 . 32 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 33 master clock control register (mclkctl): 0x8f ? 0x0a table 17: the mclkctl register msb lsb hsoen kben scen usben 32ken mct.2 mct.1 mct.0 bit symbol function mclkctl.7 hsoen high-speed oscillator enable. when set = 1, disables the high-speed crystal oscillator and vco/pll system . this bit is not changed when the pwrdn bit is set but the oscillator/vc o/pll is disabled. the hsoen bit should never be set under normal circumstances. power down control should only be initiated via use of the pwrdn bit in misctl0 . mclkctl.6 kben 1 = disable the keypad logic clock. this bit is not changed in pwrdn mode but the function is disabled. mclkctl.5 scen 1 = disable the smart card logic clock. this bit is not changed in pwrdn mode but the function is disabled. inte rrupt logic for card insertion/removal remains operable even with smart card clock disabled. mclkctl.4 usben 1 = disable the usb logic clock. this bit is not changed in pwrdn mode but the function is disabled. mclkctl.3 32ken 1 = disable the 32khz oscillator. th is function is not affected by pwrdn mode. note: this bit must be set if there is no 32khz crystal. some internal clocks and circuits will not run if the oscillator is enabled and no crystal is connected. mclkctl.2 mct.2 this value determines the ra tio of the vco frequency (mclk) to the high- speed crystal oscillator frequency such that: mclk = (mcount*2 + 4)*fxtal. the default value is mcount = 2h such that mclk = (2*2 + 4)*12.00mhz = 96mhz. mclkctl.1 mct.1 mclkctl.0 mct.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 power control register 0 (pcon): 0x87 ? 0x00 the smod bit used for the baud rate gener ator is setup via this register. table 18: the pcon register msb lsb smod C C C gf1 gf0 stop idle bit symbol function pcon.7 smod if sm0d = 1, the baud rate is doubled. pcon.6 C pcon.5 C pcon.4 C pcon.3 gf1 general purpose flag 1. pcon.2 gf0 general purpose flag 1. pcon.1 stop sets cpu to stop mode. pcon.0 idle sets cpu to idle mode. 34 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 35 1.7.5 interrupts the 80515 core provides 10 interrupt sources with f our priority levels. each source has its own request flag(s) located in a special function register ( tcon , ircon , and scon ). each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in sfrs ien0 , ien1 , and ien2 . some of the 10 sources are multiplexed in order to expand the number of interrupt sources. these will be described in more detail in the respective sections. external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 73s1217f, for example the usb interf ace, usr i/o, rtc, smart card interface, analog comparators, etc. the external interrupt configuration is shown in figure 9. . usr int ctl usr int ctl usr int ctl scint wait tim eout card event rxdata tx_event tx_sent tx_error rx_error card_det vcc_ok crdctl vccc tl + scie vcc_tmr rtc usb an a lo g comp keypad i 2 c usr int ctl t0 t1 int0 int1 usr pads usr0 usr7 usr6 usr5 usr4 usr3 usr2 usr1 int2 int3 int pads int2 int3 serial ch 0 serial ch 1 serchan 0 int serchan 1 int int4 int5 ctl int6 ctl int5 int6 + during stop, idle when pwrdn bit is set mpu core vd d _ fa u lt + delay clear pwrdn bit pdmuxctl 1 0 figure 9: external interrupt configuration downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.5.1 interrupt overview when an interrupt occurs, the mpu will vector to the predetermined address as shown in table 32 . once the interrupt service has begun, it can only be interrupt ed by a higher priority interrupt. the interrupt service is terminated by a return from the reti in struction. when an reti is performed, the processor will return to the instruction that woul d have been next when the interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by setting a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, then samples are polled by the hardw are. if the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. on the next instruction cycle, the interrupt will be acknowledged by hardware forci ng an lcall to the appropriate vector address. interrupt response will require a varying amount of time depending on the stat e of the mpu when the interrupt occurs. if the mpu is performing an interr upt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on the current instruction. the fastest possible response to an interrupt is 7 mach ine cycles. this includes one machine cycle for detecting the interrupt and six cycles to perform the lcall. 1.7.5.2 special function registers for interrupts interrupt enable 0 register (ien0): 0xa8 ? 0x00 table 19: the ien0 register msb lsb eal wdt C es0 et1 ex1 et0 ex0 bit symbol function ien0.7 eal eal = 0 C disable all interrupts. ien0.6 wdt not used for interrupt control. ien0.5 C ien0.4 es0 es0 = 0 C disable serial channel 0 interrupt. ien0.3 et1 et1 = 0 C disable timer 1 overflow interrupt. ien0.2 ex1 ex1 = 0 C disable external interrupt 1. ien0.1 et0 et0 = 0 C disable timer 0 overflow interrupt. ien0.0 ex0 ex0 = 0 C disable external interrupt 0. 36 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 37 interrupt enable 1 register (ien1): 0xb8 ? 0x00 table 20: the ien1 register msb lsb C swdt ex6 ex5 ex4 ex3 ex2 C bit symbol function ien1.7 C ien1.6 swdt not used for interrupt control. ien1.5 ex6 ex6 = 0 C disable external interrupt 6. ien1.4 ex5 ex5 = 0 C disable external interrupt 5. ien1.3 ex4 ex4 = 0 C disable external interrupt 4. ien1.2 ex3 ex3 = 0 C disable external interrupt 3. ien1.1 ex2 ex2 = 0 C disable external interrupt 2. ien1.0 C interrupt enable 2 register (ien2): 0x9a ? 0x00 table 21: the ien2 register msb lsb C C C C C C C es1 bit symbol function ien2.0 es1 es1 = 0 C disable serial channel interrupt. downloaded from: http:///
73s1217f data sheet ds_1217f_002 timer/counter control register (tcon): 0x88 ? 0x00 table 22: the tcon register msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. tcon.6 tr1 not used for interrupt control. tcon.5 tf0 timer 0 overflow flag. tcon.4 tr0 not used for interrupt control. tcon.3 ie1 interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed. clear ed when an interrupt is processed. tcon.2 it1 interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for input pin to cause an interrupt. tcon.1 ie0 interrupt 0 edge flag is set by hardware when the falling edge on external interrupt int0 is observed. clear ed when an interrupt is processed. tcon.0 it0 interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input pin to cause interrupt. timer/interrupt 2 control register (t2con): 0xc8 ? 0x00 table 23: the t2con register msb lsb C i3fr i2fr C C C C C bit symbol function t2con.7 C t2con.6 i3fr external interrupt 3 failing/rising edge flag. i3fr = 0 external interrupt 3 negative transition active. i3fr = 1 external interrupt 3 positive transition active. t2con.5 i2fr external interrupt 3 failing/rising edge flag. i2fr = 0 external interrupt 3 negative transition active. i2fr = 1 external interrupt 3 positive transition active. t2con.4 C t2con.3 C t2con.2 C t2con.1 C t2con.0 C 38 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 39 interrupt request register (ircon): 0xc0 ? 0x00 table 24: the ircon register msb lsb C C ex6 iex5 iex4 iex3 iex2 C bit symbol function ircon.7 C ircon.6 C ircon.5 iex6 external interrupt 6 flag. ircon.4 iex5 external interrupt 5 flag. ircon.3 iex4 external interrupt 4 flag. ircon.2 iex3 external interrupt 3 flag. ircon.1 iex2 external interrupt 2 flag. ircon.0 C 1.7.5.3 external interrupts the external interrupts (external to t he cpu core) are connected as shown in table 25 . interrupts with multiple sources are ored together and individual interrupt source control is pr ovided in xram sfrs to mask the individual interrupt sources and provide t he corresponding interrupt flags. multifunction usr [7:0] pins control interrupts 0 and 1. dedicated exter nal interrupt pins int2 and int3 control interrupts 2 and 3. the polarity of interrupts 2 and 3 is programmabl e in the mpu. interrupts 4, 5 and 6 have multiple peripheral sources and are multiplexed to one of these three interrupts. the peripheral functions will be described in subsequent sections. generic 80515 mpu lit erature states that interrupts 4 through 6 are defined as rising edge sensitive. thus, the hardw are signals attached to interrupts 4, 5 and 6 are converted to rising edge level by the hardware. sfr (special function register) enable bits must be se t to permit any of these interrupts to occur. likewise, each interrupt has its own flag bit that is se t by the interrupt hardware and is reset automatically by the mpu interrupt handler. table 25: external mpu interrupts external interrupt connection polarity flag reset 0 usr i/o high priority see usrintctlx automatic 1 usr i/o low priority see usrintctlx automatic 2 external interrupt pin int2 edge selectable automatic 3 external interrupt pin int3 edge selectable automatic 4 smart card interrupts n/a automatic 5 usb, rtc and keypad n/a automatic 6 i 2 c, v dd _fault, analog comp n/a automatic note: interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of the corresponding register. to prevent any interrupts from being ignored, the register containing multiple interrupt flags should be stored temporary to allow eac h interrupt flag to be tested separately to see which interrupt(s) is/are pending. downloaded from: http:///
73s1217f data sheet ds_1217f_002 table 26: control bits for external interrupts enable bit description flag bit description ex0 enable external interrupt 0 ie0 external interrupt 0 flag ex1 enable external interrupt 1 ie1 external interrupt 1 flag ex2 enable external interrupt 2 iex2 external interrupt 2 flag ex3 enable external interrupt 3 iex3 external interrupt 3 flag ex4 enable external interrupt 4 iex4 external interrupt 4 flag ex5 enable external interrupt 5 iex5 external interrupt 5 flag ex6 enable external interrupt 6 iex6 external interrupt 6 flag 1.7.5.4 power down interrupt logic the 73s1217f contains special interrupt logic to allow int0 to wake up the cpu from a power down (cpu stop) state. see the power control modes section for details. 1.7.5.5 interrupt priority level structure all interrupt sources are combined in groups, as shown in table 27 . table 27: priority level groups group 0 external interrupt 0 serial channel 1 interrupt 1 timer 0 interrupt C external interrupt 2 2 external interrupt 1 C external interrupt 3 3 timer 1 interrupt C external interrupt 4 4 serial channel 0 interrupt C external interrupt 5 5 C C external interrupt 6 each group of interrupt sources can be programmed indivi dually to one of four priority levels by setting or clearing one bit in the special function register ip0 and one in ip1. if requests of the same priority level are received simultaneously, an internal polling sequence as per table 31 determines which request is serviced first. ien enable bits must be set to permit any of these inte rrupts to occur. likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the mpu interrupt handler. interrupt priority 0 register (ip0): 0xa9 ? 0x00 table 28: the ip0 register msb lsb C wdts ip0.5 ip0.4 ip 0.3 ip0.2 ip0.1 ip0.0 note: wdts is not used for interrupt controls. 40 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 41 interrupt priority 1 register (ip1): 0xb9 ? 0x00 table 29: the ip1 register msb lsb C C ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 table 30: priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 level2 1 1 level3 (highest) table 31: interrupt polling sequence external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external interrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt serial channel 0 interrupt external interrupt 4 external interrupt 5 external interrupt 6 1.7.5.6 interrupt sources and vectors table 32 shows the interrupts with their associated flags and vector addresses. table 32: interrupt vectors interrupt request flag description interrupt vector address n/a chip reset 0x0000 ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external interrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrupt 5 0x0063 iex6 external interrupt 6 0x006b downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.6 uart the 80515 core of the 73s1217f includes two separate uarts that can be programmed to communicate with a host. the 73s1217f can only connect one uart at a time since there is only one set of tx and rx pins. the misctl0 register is used to select which uart is connected to the tx and rx pins. each uart has a different set of operating modes that t he user can select according to their needs. the uart is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 115,200 bits/s. the tx and rx pins operate at the v dd supply voltage levels and should never exceed 3.6v. the operation of each pin is as follows: rx : serial input data is applied at this pin. confor ming to rs-232 standard, the bytes are input lsb first. the voltage applied at rx must not exceed 3.6v. tx : this pin is used to output the serial data. the bytes are output lsb first. the 73s1217f has several uart-related read/write regist ers. all uart transfers are programmable for parity enable, parity select, 2 stop bits/1 stop bi t and xon/xoff options for variable communication baud rates from 300 to 115200 bps. table 47 shows the selectable uart operation modes and table 48 shows how the baud rates are calculated. table 33: uart modes uart 0 uart 1 mode 0 n/a start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) mode 1 start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu n/a mode 3 start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) n/a note: parity of serial data is available through the p fl ag of the accumulator. seven-bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting and reading bit 7 of 8-bit output data. seven-bit serial modes without parity c an be simulated by setting bit 7 to a constant 1.8-bit serial modes with parity can be simulated by se tting and reading the 9th bit, using the control bits s0con3 and s1con3 in the s0con and s1con sfrs. table 34: baud rate generation using timer 1 using internal baud rate generator serial interface 0 2 smod * f ckmpu / (384 * (256-th1)) 2 smod * f ckmpu /(64 * (2 10 -s0rel)) serial interface 1 n/a f ckmpu /(32 * (2 10 -s1rel)) note: s0rel (9:0) and s1rel (9:0) are 10-bit values der ived by combining bits from the respective timer reload registers sxrelh (bits 1:0) and sxrell (bits 7:0). th1 is the high byte of timer 1. the smod bit is located in the pcon sfr. 42 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 43 power control register 0 (pcon): 0x87 ? 0x00 the smod bit used for the baud rate gener ator is set up via this register. table 35: the pcon register msb lsb smod C C C gf1 gf0 stop idle bit symbol function pcon.7 smod if sm0d = 1, the baud rate is doubled. pcon.6 C pcon.5 C pcon.4 C pcon.3 gf1 general purpose flag 1. pcon.2 gf0 general purpose flag 1. pcon.1 stop sets cpu to stop mode. pcon.0 idle sets cpu to idle mode. baud rate control register 0 (brcon): 0xd8 ? 0x00 the bsel bit used to enable the baud rate gener ator is set up via this register. table 36: the brcon register msb lsb bsel C C C C C C C bit symbol function brcon.7 bsel if bsel = 0, the baud rate is derived using timer 1. if bsel = 1 the baud rate generator circuit is used. brcon.6 C brcon.5 C . brcon.4 C brcon.3 C brcon.2 C brcon.1 C brcon.0 C downloaded from: http:///
73s1217f data sheet ds_1217f_002 miscellaneous control register 0 (misctl0): 0xfff1 ? 0x00 transmit and receive (tx and rx) pin selection and loop back test configuration are set up via this register. table 37: the misctl0 register msb lsb pwrdn C C C C C slpbk ssel bit symbol function misctl0.7 pwrdn this bit places t he 73s1217f into a power down state. misctl0.6 C misctl0.5 C misctl0.4 C misctl0.3 C misctl0.2 C misctl0.1 slpbk 1 = uart loop back testing mode. the pins txd and rxd are to be connected together externally (w ith slpbk =1) and therefore: slpbk ssel mode 0 0 normal using serial_0 0 1 normal using serial_1 1 0 serial_0 tx feeds serial_1 rx 1 1 serial_1 tx feeds serial_0 rx misctl0.0 ssel selects either serial_1 if set =1 or serial_0 if set = 0 to be connected to rxd and txd pins. 1.7.6.1 serial interface 0 the serial interface 0 can operate in four modes: ? mode 0 pin rx serves as input and output. tx outputs the shi ft clock. eight bits are transmitted with the lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in s0con as follows: ri0 = 0 and ren0 = 1. in ot her modes, a start bit when ren0 = 1 starts receiving serial data. ? mode 1 pin rx serves as input, and tx serves as serial out put. no external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the transmission, 8 dat a bits are available by reading s0buf , and stop bit sets the flag rb80 in the special function register s0con . in mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. ? mode 2 this mode is similar to mode 1, with two differences. the baud rate is fixed at 1/32 or 1/64 of oscillator frequency and 11 bits are transmitted or received: a star t bit (0), 8 data bits (lsb first), a programmable 9th bit, and a stop bit (1). the 9th bit can be used to control the parity of the serial interface: at transmission, bit tb80 in s0con is output as the 9th bit, and at re ceive, the 9th bit affects rb80 in special function register s0con . ? mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal baud rate generator or timer 1 can be use to specify baud rate. the s0buf register is used to read/write dat a to/from the serial 0 interface. serial interface 0 control register (s0con): 0x9b ? 0x00 44 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 45 transmit and receive data are tr ansferred via this register. table 38: the s0con register msb lsb sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 bit symbol function s0con.7 sm0 these two bits set the uart0 mode: mode description sm0 sm1 0 n/a 0 0 1 8-bit uart 0 1 2 9-bit uart 1 0 3 9-bit uart 1 1 s0con.6 sm1 s0con.5 sm20 enables the inter-p rocessor communication feature. s0con.4 ren0 if set, enables serial reception. cleared by software to disable reception. s0con.3 tb80 the 9th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.). s0con.2 rb80 in modes 2 and 3 it is the 9th dat a bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0 this bit is not used. must be cleared by software. s0con.1 ti0 transmit interrupt flag, set by hardw are after completion of a serial transfer. must be cleared by software. s0con.0 ri0 receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. 1.7.6.2 serial interface 1 the serial interface 1 can operate in 2 modes: ? mode a this mode is similar to mode 2 and 3 of serial interf ace 0, 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9th bit, and a stop bit (1). the 9th bit can be used to control the parity of the serial inte rface: at transmission, bit tb81 in s1con is outputted as the 9th bit, and at receive, the 9th bit affect s rb81 in special function register s1con . the only difference between mode 3 and a is that in mode a only the in ternal baud rate generator can be use to specify baud rate. ? mode b this mode is similar to mode 1 of serial interface 0. pin rx serves as input, and tx serves as serial output. no external shift clock is used, 10 bits ar e transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a st art bit synchronizes the transmission, 8 data bits are available by reading s1buf , and stop bit sets the flag rb81 in the special function register s1con . in mode 1, the internal baud rate generator is use to specify the baud rate. the s1buf register is used to read/write dat a to/from the serial 1 interface. downloaded from: http:///
73s1217f data sheet ds_1217f_002 serial interface control register (s1con): 0x9b ? 0x00 the function of the serial port depends on the setting of the serial port control register s1con. table 39: the s1con register msb lsb sm C sm21 ren1 tb81 rb81 ti1 ri1 bit symbol function s1con.7 sm sets the uart operation mode. sm mode description baud rate 0 a 9-bit uart variable 1 b 8-bit uart variable s1con.6 C s1con.5 sm21 enables the inter-p rocessor communication feature. s1con.4 ren1 if set, enables serial recept ion. cleared by software to disable reception. s1con.3 tb81 the 9th transmitted data bit in mode a. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.). s1con.2 rb81 in mode b, if sm21 is 0, rb81 is the stop bit. must be cleared by software. s1con.1 ti1 transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software. s1con.0 ri1 receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. multiprocessor operation mode: the feature of receiving 9 bits in modes 2 and 3 of serial interface 0 or in mode a of serial interface 1 can be used for mu ltiprocessor communication. in this case, the slave processors have bit sm20 in s0con or sm21 in s1con set to 1. when the master processor outputs slaves address, it sets the 9th bit to 1, causing a seri al port receive interrupt in all the slaves. the slave processors compare the received byte with their net work address. if there is a match, the addressed slave will clear sm20 or sm21 and receive the rest of the message, while other slaves will leave the sm20 or sm21 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves. 46 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 47 1.7.7 timers and counters the 80515 has two 16-bit timer/counter registers: timer 0 and timer 1. these registers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12 periods of the mpu clock signal. in counter mode, the register is incremented when the falling edge is observed at the corresponding input signal t0 or t1 (t0 and t1 are the timer gati ng inputs derived from us r[0:7] pins, see the user (usr) ports section). since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input s hould be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function registers ( tmod and tcon ) are used to select the appropriate mode. the timer 0 load registers are designated as tl0 and th0 and the timer 1 load registers are designated as tl1 and th1. timer/counter mode control register (tmod): 0x89 ? 0x00 table 40: the tmod register msb lsb gate c/t m1 m0 gate c/t m1 m0 timer 1 timer 0 bits tr1 and tr0 in the tcon register start their associated timers when set. bit symbol function tmod.7 tmod.3 gate if set, enables external gate control (usr pin(s) connected to t0 or t1 for counter 0 or 1, respectively). when t0 or t1 is high, and trx bit is set (see the tcon register), a counter is incremented every falling edge on t0 or t1 input pin. if not set, the trx bit controls the corresponding timer. tmod.6 tmod.2 c/t selects timer or counter operati on. when set to 1, the counter operation is performed based on the falling edge of t0 or t1. when cleared to 0, the corresponding register will function as a timer. tmod.5 tmod.1 m1 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. tmod.4 tmod.0 m0 selects the mode for timer/counter 0 or timer/counter 1, as shown in tmod description. downloaded from: http:///
73s1217f data sheet ds_1217f_002 table 41: timers/counters mode description m1 m0 mode function 0 0 mode 0 13-bit counter/timer. 0 1 mode 1 16-bit counter/timer. 1 0 mode 2 8-bit auto-reload counter/timer. 1 1 mode 3 if timer 1 m1 and m0 bits are set to 1, timer 1 stops. if timer 0 m1 and m0 bits are set to 1, time r 0 acts as two independent 8-bit timer/counters. mode 0 putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag tf0. the overflow flag tf0 then can be used to request an interrupt. the counted input is enabled to the timer w hen trx = 1 and either gate = 0 or tx = 1 (setting gate = 1 allows the timer to be controlled by external input tx, to facilitate pulse width measurements). trx are control bits in t he special function register tcon ; gate is in tmod . the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl0. the upper 3 bits of tl0 are indeterminate and should be ignored. setting the run flag (trx) does not clear the r egisters. mode 0 operation is the same for timer 0 as for timer 1. mode 1 mode 1 is the same as mode 0, except that the timer register is run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tlx) with automatic reload. the overflow from tlx not only sets tfx, but also reloads tlx with the c ontents of thx, which is preset by software. the reload leaves thx unchanged. mode 3 mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr 1 and tf1 from timer 1. thus, th0 now controls the "timer 1" interrupt. mode 3 is provided for applic ations requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate gener ator, or in fact, in any application not requiring an interrupt from timer 1 itself. 48 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 49 timer/counter control register (tcon): 0x88 ? 0x00 table 42: the tcon register msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function tcon.7 tf1 the timer 1 overflow flag is set by hardware when timer 1 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon.6 tr1 timer 1 run control bit. if cleared, timer 1 stops. tcon.5 tf0 timer 0 overflow flag set by hardwar e when timer 0 overflows. this flag can be cleared by software and is automatically cleared when an interrupt is processed. tcon.4 tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon.3 ie1 external interrupt 1 edge flag. tcon.2 it1 external interrupt 1 type control bit. tcon.1 ie0 external interrupt 0 edge flag. tcon.0 it0 external interrupt 0 type control bit. 1.7.8 wd timer (software watchdog timer) the software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. after a reset, the watchdog timer is disabled and all registers are set to zero. the watchdog consists of a 16-bit counter (wdt), a reload register ( wdtrel ), prescalers (by 2 and by 16), and control logic. once the watchdog starts, it cannot be stopped unless t he internal reset signal becomes active. note: it is recommended to use the hardware watchdog timer instead of the software watchdog timer (refer to the rtc description ). wd timer start procedure: the wdt is started by setting the swdt flag. when the wdt register enters the state 0x7cff, an asynchr onous wdts signal will become active. the signal wdts sets bit 6 in the ip0 register and requests a reset state. wdts is cleared either by the reset signal or by changing the state of the wdt timer. refreshing the wd timer: the watchdog timer must be refreshed r egularly to prevent the reset request signal from becoming active. this requirement im poses an obligation on the programmer to issue two instructions. the first instruction sets wdt and t he second instruction sets swdt. the maximum delay allowed between setting wdt and swdt is 12 clock cy cles. if this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt is automatically reset. downloaded from: http:///
73s1217f data sheet ds_1217f_002 interrupt enable 0 register (ien0): 0xa8 ? 0x00 table 43: the ien0 register msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 bit symbol function ien0.7 eal eal = 0 C disable all interrupts. ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watc hdog timer. must be set directly before swdt is set to prevent an unintentional refresh of the watchdog timer. wdt is reset by hardware 12 clock cycles after it has been set. ien0.5 C ien0.4 es0 es0 = 0 C disable serial channel 0 interrupt. ien0.3 et1 et1 = 0 C disable timer 1 overflow interrupt. ien0.2 ex1 ex1 = 0 C disable external interrupt 1. ien0.1 et0 et0 = 0 C disable timer 0 overflow interrupt. ien0.0 ex0 ex0 = 0 C disable external interrupt 0. interrupt enable 1 register (ien1): 0xb8 ? 0x00 table 44: the ien1 register msb lsb C swdt ex6 ex5 ex4 ex3 ex2 bit symbol function ien1.7 C ien1.6 swdt watchdog timer start/refresh fl ag. set to activate/refresh the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. bit swdt is reset by the hardware 12 clock cycles after it has been set. ien1.5 ex6 ex6 = 0 C disable external interrupt 6. ien1.4 ex5 ex5 = 0 C disable external interrupt 5. ien1.3 ex4 ex4 = 0 C disable external interrupt 4. ien1.2 ex3 ex3 = 0 C disable external interrupt 3. ien1.1 ex2 ex2 = 0 C disable external interrupt 2. ien1.0 C 50 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 51 interrupt priority 0 register (ip0): 0xa9 ? 0x00 table 45: the ip0 register msb lsb C wdts ip0.5 ip0.4 ip 0.3 ip0.2 ip0.1 ip0.0 bit symbol function ip0.6 wdts watchdog timer status flag. set when the watchdog timer has expired. the internal reset will be generated, but this bit will not be cleared by the reset. this allows the user progr am to determine if the watchdog timer caused the reset to occur and respond accordingly. can be read and cleared by software. note: the remaining bits in the ip0 r egister are not used for watchdog control. watchdog timer reload register (wdtrel): 0x86 ? 0x00 table 46: the wdtrel register msb lsb wdpsel wdrel6 wdrel5 wdrel4 wdrel3 wdrel2 wdrel1 wdrel0 bit symbol function wdtrel.7 wdpsel prescaler select bit. when set, the watchdog is clocked through an additional divide-by-16 prescaler. wdtrel.6 to wdtrel.0 wdrel6-0 seven bit reload value for the high-byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt. downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.9 user (usr) ports the 73s1217f includes 8 pins of general purpose digital i/o (gpio). on reset or power-up, all usr pins are inputs until they are configured for the desired direction. the pi ns are configured and controlled by the usr70 and udir70 sfrs. each pin declared as usr can be configured independently as an input or output with the bits of the udir70 register. table 47 lists the direction registers and configurability associated with each group of usr pins. usr pins 0 to 7 are multiple use pins that can be used for general purpose i/o, external interrupts and timer control. table 48 shows the configuration for a usr pin through its associated bit in its udir register. values read from and written into the gpio ports use the data registers usr70 . note: after reset, all usr pins are defaulted as inputs and pulled up to vdd until any write to the corresponding udir register is performed. this insures all usr pins are set to a known value until set by the firmware. unused usr pins can be set for output if unused and unconnected to pr event them from floating. alternatively, unused usr pins can be set for input and tied to ground or v dd . table 47: direction registers and internal resources for dio pin groups usr pin group type direction register name direction register (sfr) location data register name data register (sfr) location usr_0usr_7 multi-use udir70 0x91 [7:0] usr70 0x90 [7:0] table 48: udir control bit udir bit 0 1 usr pin function output input four xram sfr registers ( usrintctl1 , usrintctl2 , usrintctl3 , and usrintctl4 ) control the use of the usr [7:0] pins. each of the usr [7:0] pins c an be configured as gpio or individually be assigned an internal resource such as an interrupt or a timer/counter control. each of the four registers contains two 3-bit configuration words named uxis (where x corre sponds to the usr pin). the control resources selectable for the usr pins are listed in table 74 through table 78. if more than one input is connected to the same resource, the resources are combined using a logical or. table 49: selectable controls using the uxis bits uxis value resource selected for usrx pin 0 none 1 none 2 t0 (counter0 gate/clock) 3 t1 (counter1 gate/clock) 4 interrupt 0 rising edge/high level on usrx 5 interrupt 1 rising edge/high level on usrx 6 interrupt 0 falling edge/low level on usrx 7 interrupt 1 falling edge/low level on usrx note: x denotes the corresponding usr pin. interrupt edge or level control is assigned in the it0 and it1 bits in the tcon register. 52 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 53 external interrupt control register (usrintctl1) : 0xff90 ? 0x00 table 50: the usrintctl1 register msb lsb C u1is.6 u1is.5 u1is.4 C u0is.2 u0is.1 u0is.0 external interrupt control register (usrintctl2) : 0xff91 ? 0x00 table 51: the usrintctl2 register msb lsb C u3is.6 u3is.5 u3is.4 C u2is.2 u2is.1 u2is.0 external interrupt control register (usrintctl3) : 0xff92 ? 0x00 table 52: the usrintctl3 register msb lsb C u5is.6 u5is.5 u5is.4 C u4is.2 u4is.1 u4is.0 external interrupt control register (usrintctl4) : 0xff93 ? 0x00 table 53: the usrintctl4 register msb lsb C u7is.6 u7is.5 u7is.4 C u6is.2 u6is.1 u6is.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.10 real-time clock with hardware watchdog (rtc) figure 10 shows the block diagram of the real time clock. the rtc block uses the 32768hz oscillator signal and divider logic to produce 0.5-second time mar ks. the time marks are used to create interrupts at intervals from 0.5 seconds to 8 seconds as selected by rtc interval (rtcinv(2:0)). the 32768hz oscillator can be disabled but is intended to operate at all times and in all power consumption modes. if a 32khz crystal is not provided, the 32 khz osc illator should be disabled and the rtc will operate from mclk (96mhz) divided by 2930 (refer to the osc illator and clock generation section). the clock generated by the high speed oscillator will not yiel d exactly 32768 hz, but a frequency of approximately 32764.505119 hz. this yields a negative 106.6 ppm (1 / 9375) error with respect to 32768hz. the rtc circuit provides hardware to compensate for this erro r by providing an offset circuit that will adjust the rtc counter. adder 23 bit trim value 24 bit accumulator select interrupt rate divider 1/2 second 1 second 2 second 4 second 8 second select count rate 32 bit counter overflow sign advance r/w bus r/w bus rtc int r/w bus r/w bus r/w bus 1/2 1 2 1/2 1 24 8 if k overflow* sign=0, extra count if k overflow* sign=1, skip one count 1.024khz clock watch dog timer reset start rtc isr wdt_timeout 1/2s timeout rtcclk figure 10: real time clock block diagram 54 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 55 a 32-bit rtc counter is clocked by a selectable clo ck (1/2, 1, 2 second) to measure time. a trimming function is provided such that a trim value is accumulated in a 24-bit accumulator at the same rate as the rtc counter. the trim value is sign magnitude number . when the accumulator reaches overflow, it will advance the counter one additional count if the trim value is positive, or prevent the counter from advancing one count if the trim value is negative. th is mechanism allows the rtc counter to be adjusted to keep accurate time with a minimum 0.5 second resolution. when using the high speed oscillator, the rtc counter wants to have an extra count added every 9375 seconds to keep the rtc counter at the proper time. if the one second rtc counter rate is used, the rtc trim value should be set to 0x6fd (1789 decimal). this value is derived by taking t he resolution of the 24 bit accumulator (2 ^ 24 = 16777216) and dividing this by 9375. this means the rtc accumulator will overflow every 9375 seconds and will cause the rtc counter to advance by 2 when t he accumulator overflow occurs, thus bringing the rtc count to the proper time. in addition to the basic software watchdog timer included in the 80515 mpu, an independent, robust, fixed-duration, hardware watchdog timer (wdt) is included with the 73s1217f rtc. the watch dog timer will give the mpu ? second to respond to the rtc interrupt. if the processor does not perform an rtc interrupt service, a full reset will be performed. the rtc interrupt is connected to the core interrupt external interrupt 5 signal. the rtc interrupt must be enabled to obtain the watchdog timer function. note: if the power down mode doesnt want the watchdog to wake up the mpu, the rtc interrupt should be masked before entering the power down mode. real time clock control register (rtcctl) : 0x ffb0 ? 0x00 table 54: the rtcctl register msb lsb C C rtcld ctsel.1 ctsel.0 rint.2 rint.1 rint.0 bit symbol function rtcctl.7 C rtcctl.6 C rtcctl.5 rtcld when set, rtc parameters (rtc count, rtc accumulator, and rtc trim) are loaded at the next 32khz clock positive edge. rtcctl.4 ctsel.1 selects the time value that is counted by the real time clock: 0x C 1 second (default) 10 C ? second 11 C 2 seconds rtcctl.3 ctsel.0 rtcctl.2 rint.2 rtc interrupt internal selection bits: (listed as bits 2,1,0) 100 C 0.5 second 0xx C 1 second (default) 101 C 2 seconds 110 C 4 seconds 111 C 8 seconds rtcctl.1 rint.1 rtcctl.0 rint.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 there are 3 sets of registers to load the rtc 24-bit a ccumulator, 32-bit counter and 23-bit trim registers. the registers are loaded when the rtcld bit is set in rtcctl . table 55: the 32-bit rtc counter register rtccnt3 rtccnt2 rtccnt1 rtccnt0 rtccnt[31:24] rtccnt[23:16] rtccnt[15:8] rtccnt[7:0] table 56: the 24-bit rtc accumulator register rtcacc2 rtcacc1 rtcacc0 rtcacc [23:16] rtca cc [15:8] rtcacc [7:0] table 57: the 24-bit rtc trim (sign magnitude value) register rtctrim2 rtctrim1 rtctrim0 rtctrim [23:16] rtctrim [15:8] rtctrim [7:0] external interrupt control register (int5ctl): 0xff94 ? 0x00 table 58: the int5ctl register msb lsb pdmux C rtcien rtcint usbien usbint kpien kpint bit symbol function int5ctl.7 pdmux power down multiplexer control. int5ctl.6 C int5ctl.5 rtcien when set =1, enables rtc interrupt. note: the rtc based watchdog will be enabled when set. int5ctl.4 rtcint when set =1, indicates interrupt from real time clock function. cleared on read of register. int5ctl.3 usbien usb interrupt enable. int5ctl.2 usbint usb interrupt flag. int5ctl.1 kpien keypad interrupt enable. int5ctl.0 kpint keypad interrupt flag. 56 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 57 1.7.11 analog voltage comparator the 73s1217f includes a programmable comparator t hat is connected to the ana_in pin. the comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. the comparator control register should not be modified when the analog interrupt (anaien bit in the int6ctl register) is enabled to guard against any false interrupt that might be generated when modifying the threshold. the compar ator has a built-in hysteresis to prevent the comparator from repeatedly responding to low-amplitude noise. this hysteresis is approximately 20mv. the maximum voltage on the ana_in pad should be less than 3 volts. an external resistor divider is required for detecting voltages greater than 3.0 volts. interrupt control is handled in the int6ctl register. analog compare control register (acomp): 0xffd0 ? 0x00 table 59: the acomp register msb lsb analvl C onchg cpol cmpen 0 tsel.1 tsel.0 bit symbol function acomp.7 analvl when read, indicates whether the input level is above or below the threshold. this is a real time va lue and is not latched, so it may change from the time of the interrupt trigger until read. acomp.6 C acomp.5 onchg if set, the ana_interrupt is invoked on any change above or below the threshold, bit 4 is ignored. acomp.4 cpol if set = 1, ana_interrupt is invo ked when signal rises above selected threshold. if set = 0, ana_interr upt is invoked when signal goes below selected threshold (default). acomp.3 cmpen enables power to the analog comparator. 1= enabled. 0 = disabled (default). acomp.2 0 this value must be fixed at 0. acomp.1 tsel.1 sets the voltage threshold for compar ison to the voltage on pin ana_in. thresholds are as follows: 00 = 1.00v 01 = 1.24v 10 = 1.40v 11 = 1.50v acomp.0 tsel.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 external interrupt control register (int6ctl): 0xff95 ? 0x00 table 60: the int6ctl register msb lsb C C vftien vftint i2cien i2cint anien anint bit symbol function int6ctl.7 C int6ctl.6 C int6ctl.5 vftien vdd fault interrupt enable. int6ctl.4 vftint vdd fault interrupt flag. int6ctl.3 i2cien i 2 c interrupt enabled. int6ctl.2 i2cint i 2 c interrupt flag. int6ctl.1 anien if anien = 1 analog compare event interrupt is enabled. when masked (anien = 0), anint (bit 0) may be set, but no interrupt is generated. int6ctl.0 anint (read only) set when the selected ana_in signal changes with respect to the selected threshold if compare_enable is asserted. cleared on read of register. 58 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 59 1.7.12 led driver the 73s1217f provides a single dedicated output pin fo r driving an led. the led driver pin can be configured as a current source that will pull to gr ound to drive an led that is connected to vdd without the need for an external current limiting resistor. this pin may be used as general purpose output with the programmed pull-down current and a strong (cmos) pull-up, if enabled. the analog block must be enabled when this output is being used to drive the selected output current. this pin may be used as an input with considerati on of the programmed output current and level. the register bit when read, indica tes the state of the pin. led control register (ledctl): 0xfff3 ? 0xff table 61: the ledctl register msb lsb C lpuen iset.1 iset.0 ledd3 ledd2 ledd 1 ledd0 bit symbol function ledctl.7 C ledctl.6 lpuen 0 = pull-up is enabled for the led pin. ledctl.5 iset.1 these two bits control the drive current (to ground) for the led driver pin. current levels are: 00 = 0ma(off) 01 = 2ma 10 = 4ma 11 = 10ma ledctl.4 iset.0 ledctl.3 C ledctl.2 C ledctl.1 C ledctl.0 ledd0 write data controls output level of pin led0. read will report level of pin led0. downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.13 i 2 c master interface the 73s1217f includes a dedicated fast mode, 400khz i 2 c master interface. the i 2 c interface can read or write 1 or 2 bytes of data per data transfer frame. the mpu communicates with the interface through six dedicated sfr registers: ? device address ( dar ) ? write data ( wdr ) ? secondary write data ( swdr ) ? read data ( rdr ) ? secondary read data ( srdr ) ? control and status ( csr ) the dar register is used to set up the slave address and specify if the transacti on is a read or write operation. the csr register sets up, starts the transaction and reports any errors that may occur. when the i 2 c transaction is complete, the i 2 c interrupt is reported via external interrupt 6. the i 2 c interrupt is automatically de-asserted when a subsequent i 2 c transaction is started. the i 2 c interface uses a 400khz clock from the time-base circuits. 1.7.13.1 i 2 c write sequence to write data on the i 2 c master bus, the 80515 has to program t he following registers according to the following sequence: 1. write slave device address to device address register ( dar ). the data contains 7 bits for the slave device address and 1 bit of op-code. the op-code bit s hould be written with a 0 to indicate a write operation. 2. write data to write data register ( wdr ). this data will be transferred to the slave device. 3. if writing 2 bytes, set bit 0 of the control and status register ( csr ) and load the second data byte to secondary write data register ( swdr) . 4. set bit 1 of the csr register to start i 2 c master bus. 5. wait for i 2 c interrupt to be asserted. it indicates that the write on i 2 c master bus is done. refer to information about the int6ctl , ien1 and ircon register for masking and flag operation. 60 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 61 figure 11 shows the timing of the i 2 c write mode. 1-7 8 9 10-17 18 ack bit ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] write data [7:0 i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) 1-7 8 9 10-17 18 ack bit ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] write data [7:0] i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) secondary write data [7:0] ack bit 19-26 27 lsb msb figure 11: i 2 c write mode operation 1.7.13.2 i 2 c read sequence to read data on the i 2 c master bus from a slave device, the 80515 has to program the following registers in this sequence: 1. write slave device address to the device address register ( dar ). the data contains 7 bits device address and 1 bit of op-code. the op-code bit should be written with a 1. 2. write control data to the control and status register ( csr ). write a 1 to bit 1 to start i 2 c master bus. also write a 1 to bit 0 if the secondary read data register ( srdr ) is to be captured from the i 2 c slave device. 3. wait for i 2 c interrupt to be asserted. it indi cates that the read operation on the i 2 c bus is done. refer to information about the int6ctl , ien1 and ircon registers for masking and flag operation. 4. read data from the read data register ( rdr ). 5. read data from secondary read data register ( srdr ) if bit 0 of control and status register ( csr ) is written with a 1. downloaded from: http:///
73s1217f data sheet ds_1217f_002 62 rev. 1.2 the following diagram shows the timing of the i 2 c read mode. 1-7 8 9 10-17 18 ack bit no ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] read data [7:0 i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) 1-7 8 9 10-17 18 ack bit no ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] read data [7:0] i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) secondary read data[7:0] ack bit 19-26 27 figure 12: i 2 c read operation downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 63 device address register (dar): 0xff80 ? 0x00 table 62: the dar register msb lsb dvadr.6 dvadr.5 dvadr.4 dvadr. 3 dvadr.2 dvadr.1 dvadr.0 i2crw bit symbol function dar.7 dvadr [0:6] slave device address. dar.6 dar.5 dar.4 dar.3 dar.2 dar.1 dar.0 i2crw if set = 0, the transaction is a write operation. if set = 1, read. i2c write data register (wdr): 0xff81 ? 0x00 table 63: the wdr register msb lsb wdr.7 wdr.6 wdr.5 wdr.4 wdr.3 wdr.2 wdr.1 wdr.0 bit function wdr.7 data to be written to the i 2 c slave device. wdr.6 wdr.5 wdr.4 wdr.3 wdr.2 wdr.1 wdr.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 i2c secondary write data register (swdr): 0xff82 ? 0x00 table 64: the swdr register msb lsb swdr.7 swdr.6 swdr.5 swdr.4 swdr.3 swdr.2 swdr.1 swdr.0 bit function swdr.7 second data byte to be written to the i 2 c slave device if bit 0 (i 2clen) of the control and status register ( csr ) is set = 1. swdr.6 swdr.5 swdr.4 swdr.3 swdr.2 swdr.1 swdr.0 i2c read data register (rdr): 0xff83 ? 0x00 table 65: the rdr register msb lsb rdr.7 rdr.6 rdr.5 rdr.4 rdr.3 rdr.2 rdr.1 rdr.0 bit function rdr.7 data read from the i 2 c slave device. rdr.6 rdr.5 rdr.4 rdr.3 rdr.2 rdr.1 rdr.0 64 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 65 i2c secondary read data register (srdr): 0xff84 ? 0x00 table 66: the srdr register msb lsb srdr.7 srdr.6 srdr. 5 srdr.4 srdr.3 s rdr.2 srdr.1 srdr.0 bit function srdr.7 second data byte to be read from the i 2 c slave device if bit 0 (i 2clen) of the control and status register ( csr ) is set = 1. srdr.6 srdr.5 srdr.4 srdr.3 srdr.2 srdr.1 srdr.0 i2c control and status register (csr): 0xff85 ? 0x00 table 67: the csr register msb lsb C C C C C akerr i2cst i2clen bit symbol function csr.7 C csr.6 C csr.5 C csr.4 C csr.3 C csr.2 akerr set to 1 if acknowledge bit from slave de vice is not 0. automatically reset when the new bus transaction is started. csr.1 i2cst write a 1 to start i 2 c transaction. automatically reset to 0 when the bus transaction is done. this bit should be treated as a busy indicator on reading. if it is high, the serial r ead/write operations are not completed and no new address or data should be written. csr.0 i2clen set to 1 for 2-byte read or writ e operations. set to 0 for 1-byte operations. downloaded from: http:///
73s1217f data sheet ds_1217f_002 external interrupt control register (int6ctl): 0xff95 ? 0x00 table 68: the int6ctl register msb lsb C C vftien vftint i2cien i2cint anien anint bit symbol function int6ctl.7 C int6ctl.6 C int6ctl.5 vftien vdd fault interrupt enable. int6ctl.4 vftint vdd fault interrupt flag. int6ctl.3 i2cien when set = 1, the i 2 c interrupt is enabled. int6ctl.2 i2cint when set =1, the i 2 c transaction has completed. cleared upon the start of a subsequent i 2 c transaction. int6ctl.1 anien analog compare interrupt enable. int6ctl.0 anint analog compare interrupt flag. 66 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 67 1.7.14 keypad interface the 73s1217f supports a 30-button (6 row x 5 column) keypad (spst mechanical contact switches) interface using 11 dedicated i/o pins. figure 13 shows a simplified block diagram of the keypad interface. scan pull-up debouncing debounce time 7 6 5 4 3 2 1 0 ksize register 6 (1) kcol is normally used as read only register. when hardware keyscan mode is disabled, this register is to be used by firmware to write the column data to handle firmware scanning. (2) 1khz internal clock signal can be selected either from the pll (= from the 12mhz main clock), or from the 32khz system clock. key_detect hardware scan enable 6 column scan order 5 column value row value key_detect_enable korderl / h registers 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 kcol register (1) 7 6 5 4 3 2 1 0 krow register dividers 1khz (2) scan time kscan register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 kstat register keypad clock keypad clock vdd pull- up col4:0 row5:0 73s1217f if smaller keypad than 6x 5 is to be implemented, unused row inputs should be connected to vdd. unused column outputs should be left unconnected. vdd figure 13: simplified keypad block diagram there are five drive lines (outputs) corresponding to columns and six sense lines (inputs) corresponding to rows. hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external resistors in the keypad. key scanning happens by asserting one of the 5 column lines low and looking for a low on a sense line indicating that a key is pressed (s witch closed) at the inters ection of the drive/sense (column/row) line in the keypad. key detection is performed by hardware with an incorporated debounce timer. debouncing time is adjustable through the kscan register. internal hardware circuitry performs downloaded from: http:///
73s1217f data sheet ds_1217f_002 column scanning at an adjustable scanning rate and column scanning order through registers kscan and korderl / korderh . key scanning is disabled at reset and must be enabled by firmware. when a valid key is detected, an interrupt is generated and t he valid value of the pressed key is automatically written into the kcol and krow registers. the keypad interface us es a 1khz clock derived from either the 32768hz crystal or the 12mhz crystal. the selection of the clock source is made external to this block, by setting bit 3 C 32kben C in the mclkctl register, see the oscillator and clock generation section). disabling the 32khz oscillator will source the 1khz clock from the 12mhz main oscillator and divide it down. setting bit 6 C kben C in the mclkctl register will enable keypad scanning and debouncing. the keypad size can be adjusted within the ksize register. normal scanning is performed by hardware w hen the bit scnen is set at 1 in the kstat register. figure 14 shows the flowchart of how the hardware scanning operates. in order to minimize power, scanning does not occur until a key-press is detected. once hardware key scanning is enabled, the hardware drives all column outputs low and waits for a low to be detected on one of the inputs. when a low is detected on any row, and before key scanning starts, the hardware checks that the low level is still detected after a debounce time. the debounce time is defined by firmware in the kscan register (bits 7:0, dbtime). debounce times from 4ms to 256ms in 4ms increments are supported. if a key is not pressed after the debounce time, the hardware will go back to looking for any input to be low. if a key is confirmed to be pressed, key scanning begins. key scanning asserts one of the 5 drive lines (col 4: 0) low and looks for a low on a sense line indicating that a key is pressed at the intersection of the drive/sense line in the keypad. after all sense lines have been checked without a key-press bei ng detected, the next column line is asserted. the time between checking each sense line is the scan time and is defined by firmware in the kscan register (bits 0:1 C sctime). scan times from 1ms to 4ms are support ed. scanning order does not affect the scan time. this scanning continues until the entire keypad is sc anned. if only one key is pressed, a valid key is detected. simultaneous key presses are not consider ed as valid (if two keys are pressed, no key is reported to firmware). possible scrambling of the column scan order is provided by means of the korderl and korderh registers that define the order of column scanning. values in these registers must be updated every time a new keyboard scan order is desired. it is not possible to change the order of scanning the sense lines. the column and row intersection for the detected valid key are stored in the kcol and krow registers. when a valid key is detected, an interrupt is generat ed. firmware can then read those registers to determine which key had been pressed. after reading the kcol and krow registers, the firmware can update the korderl / korderh registers if a new scan order is needed. when the scnen bit is enabled in the kstat register, the kcol and krow registers are only updated after a valid key has been identified. the hardware does not wait for the firmware to service the interrupt in order to proceed with the key scanning process. on ce the valid key (or invalid key C e.g. two keys pressed) is detected, the hardware waits for the ke y to be released. once the key is released, the debounce timer is started. if the key is not st ill released after the debounce time, the debounce counter starts again. after a key release, all columns will be driven low as before and the process will repeat waiting for any key to be pressed. when the scnen bit is disabled, all driv e outputs are set to the value in the kcol register. if firmware clears the scnen bit in the middle of a key scan, the kcol register contains the last value stored in there which will then be reflected on the output pins. a bypass mode is provided so that the firmware can do the key scanning manually (scnen bit must be cleared). in bypass mode, the firmware writes/reads the column and row registers to perform the key scanning. 68 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 69 figure 14: keypad interface flow chart any row input = 0 ? keypad initialization all column outputs = 0 deboucing timer any row input still = 0 ? yes no no how many keys have been detected? download of the key row and column values in krow and kcol registers 1 key keypad interrupt generation is (are) the key(s) released ? (*) deboucing timer yes is (are) the key(s) still released ? (*) no no kscan register: debouncing time kstat register: enable hw scanning enable keypad interrupt keypad scanning korderl / h registers: column scan order kstat register: key detect interrupt yes kcol register: value of the valid key column krow register: value of the valid key row kscan register: scanning rate ksize register: keypad size definition 0 key register used to control the hardware keypad interface register written by the hardware keypad interface more than 1 key kscan register: debouncing time (*) key release is cheked by looking for a low level on any row. downloaded from: http:///
73s1217f data sheet ds_1217f_002 keypad column register (kcol): 0xd1 ? 0x1f this register contains the value of the column of a key detected as valid by the hardware. in bypass mode, this register firmware writes directly this register to carry out manual scanning. table 69: the kcol register msb lsb C C C col.4 col.3 col.2 col.1 col.0 bit symbol function kcol.7 C kcol.6 C kcol.5 C kcol.4 col.4 drive lines bit mapped to corresponding with pins col(4:0). when a key is detected, firmware reads this regi ster to determine column. in bypass (s/w keyscan) mode, firmware writes this register directly. 0x1e = col(0) low, all others high. 0x0f = col(4) low, all others high. 0x1f = col(4:0) all high. kcol.3 col.3 kcol.2 col.2 kcol.1 col.1 kcol.0 col.0 keypad row register (krow): 0xd2 ? 0x3f this register contains the value of the row of a key detected as valid by the hardware. in bypass mode, this register firmware reads directly th is register to carry out manual detection. table 70: the krow register msb lsb C C row.5 row.4 row.3 row.2 row.1 row.0 bit symbol function krow.7 C krow.6 C krow.5 row.6 sense lines bit mapped to correspond with pins row(5:0). when key detected, firmware reads this register to determine row. in bypass mode, firmware reads rows and has to determine if there was a key press or not. 0x3e = row(0) low, all others high. 0x1f = row(5) low, all others high. 0x3f = row(5:0) all high. krow.4 row.4 krow.3 row.3 krow.2 row.2 krow.1 row.1 krow.0 row.0 70 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 71 keypad scan time register (kscan): 0xd3 ? 0x00 this register contains the val ues of scanning time and debouncing time. table 71: the kscan register msb lsb dbtime.5 dbtime.4 dbtime.3 dbtime.2 dbtime.1 dbtime.0 sctime.1 sctime.0 bit symbol function kscan.7 dbtime.5 de-bounce time in 4ms increments. 1 = 4ms de-bounce time, 0x3f = 252ms, 0x00 = 256ms. key presses and key releases are de-bounced by this amount of time. kscan.6 dbtime.4 kscan.5 dbtime.3 kscan.4 dbtime.2 kscan.3 dbtime.1 kscan.2 dbtime.0 kscan.1 sctime.1 scan time in ms. 01 = 1ms, 02 = 2ms, 00 = 3ms, 00 = 4ms. time between checking each key during keypad scanning. kscan.0 sctime.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 keypad control/status register (kstat): 0xd4 ? 0x00 this register is used to control the hardware ke ypad scanning and detection capabilities, as well as the keypad interrupt control and status. table 72: the kstat register msb lsb C C C C keyclk hwscen keydet kydten bit symbol function kstat.7 C kstat.6 C kstat.5 C kstat.4 C kstat.3 keyclk the current state of the keyboard clock can be read from this bit. kstat.2 hwscen hardware scan enable C when set, the hardware will perform automatic key scanning. when cleared, the firmware must perform the key scanning manually (bypass mode). kstat.1 keydet key detect C when hwscen = 1 this bi t is set causing an interrupt that indicates a valid key press was detected and the key location can be read from the keypad column and row regist ers. when hwscen = 0, this bit is an interrupt which indicates a falling edge on any row input if all row inputs had been high previously (note: multiple key detect interrupts may occur in this case due to the keypad switch bouncing). in all cases, this bit is cleared when read. when hwscen = 0 and the keypad interface 1khz clock is disabled, a key press will st ill set this bit and cause an interrupt. kstat.0 kydten key detect enable C when set, the keyd et bit can cause an interrupt and when cleared the keydet cannot caus e an interrupt. keydet can still get set even if the interrupt is not enabled. 72 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 73 keypad scan time register (ksize): 0xd5 ? 0x00 this register is not applicable when hwscen is not set. unused row inputs should be connected to vdd. table 73: the ksize register msb lsb C C rowsiz.2 rowsiz.1 rowsiz.0 colsiz.2 colsiz.1 colsiz.0 bit symbol function ksize.7 C ksize.6 C ksize.5 rowsiz.2 defines the number of rows in the keypad. maximum number is 6 given the number of row pins on the package. allows for a reduced keypad size for scanning. ksize.4 rowsiz.1 ksize.3 rowsiz.0 ksize.2 colsiz.2 defines the number of columns in the keypad. maximum number is 5 given the number of column pins on the package. allows for a reduced keypad size for scanning. ksize.1 colsiz.1 ksize.0 colsiz.0 keypad column ls scan order register (korderl): 0xd6 ? 0x00 in the korderl and korderh registers, column scan order(14:0) is grouped into 5 sets of 3 bits each. each set determines which column (col(4:0) pi n) to activate by loading the column number into the 3 bits. when in hw_scan_enable mode, the hardware will step through the sets from 1col to 5col (up to the number of columns in colsize) and scan the column defined in the 3 bits. to scan in sequential order, set a counting pattern with 0 in set 0, and 1 in set 1,and 2 in set 2, and 3 in set 3, and 4 in set 4. the firmware should update this as part of the interr upt service routine so that the new scan order is loaded prior to the next key being pressed. for ex ample, to scan col(0) first, 1col(2:0) should be loaded with 000b. to scan col(4) fifth, 5col(2:0) should be loaded with 100b. table 74: the korderl register msb lsb 3col.1 3col.0 2col.2 2col.1 2col.0 1col.2 1col.1 1col.0 bit symbol function korderl.7 3col.1 column to scan 3 rd (lsbs). korderl.6 3col.0 korderl.5 2col.2 column to scan 2 nd . korderl.4 2col.1 korderl.3 2col.0 korderl.2 1col.2 column to scan 1 st . korderl.1 1col.1 korderl.0 1col.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 keypad column ms scan order register (korderh): 0xd7 ? 0x00 table 75: the korderh register msb lsb C 5col.2 5col.1 5col.0 4col.2 4col.1 4col.0 3col.2 bit symbol function korderh.7 C korderh.6 5col.2 column to scan 5 th . korderh.5 5col.1 korderh.4 5col.0 korderh.3 4col.2 column to scan 4 th . korderh.2 4col.1 korderh.1 4col.0 korderh.0 3col.2 column to scan 3 rd (msbs). external interrupt control register (int5ctl): 0xff94 ? 0x00 table 76: the int5ctl register msb lsb pdmux C rtcien rtcint usbien usbint kpien kpint bit symbol function int5ctl.7 pdmux power down multiplexer control. int5ctl.6 C int5ctl.5 rtcien when set =1, enables rtc interrupt. int5ctl.4 rtcint when set =1, indicates interrupt from real time clock function. cleared on read of register. int5ctl.3 usbien usb interrupt enable. int5ctl.2 usbint usb interrupt flag. int5ctl.1 kpien enables keypad interrupt when set = 1. int5ctl.0 kpint this bit indicates the keypad logic has set key_detect bit and a key location may be read. cleared on read of register. 1.7.15 emulator port the emulator port, consisting of the pins e_rst, e_tclk and e_rxtx, provides control of the mpu through an external in-circuit emulator. the e_tb us[3:0] pins, together with the e_isync/brkrq, add trace capability to the emulator. the emulator port is compatible with the adm51 emulators manufactured by signum systems. if code trace capability is needed on th is interface, 20pf capacitors (to ground) need to be added to allow the trace function capability to run properly. thes e capacitors should be attached to the tbus0:3 and isbr signals. 74 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 75 1.7.16 usb interface the 73s1217f provides a single interface, fu ll speed -12mbps - usb device port as per the universal serial bus specification, revision 2.0 (backward compatible with usb 1.1). usb circuitry gathers the transceiver, the serial interface engine (sie), and the data buffers. an internal pull-up to v dd on d+ indicates that the device is a full speed device atta ched to the usb bus (allows full speed recognition by the host without adding any external components). when using the usb interface, v dd must be between 3.0v C 3.6v in order to meet the usb voh requi rement. the interface is highly configurable under firmware control. control (endpoint 0), interrupt in, bulk in and bulk out transfe rs are supported. four endpoints are supported and are configured by firmware: must be between 3.0v C 3.6v in order to meet the usb voh requi rement. the interface is highly configurable under firmware control. control (endpoint 0), interrupt in, bulk in and bulk out transfe rs are supported. four endpoints are supported and are configured by firmware: ? endpoint 0, the default (control) endpoint as required by the usb specificat ion, is used to exchange control and status information between the 73s1217f and the usb host. ? endpoint 0, the default (control) endpoint as required by the usb specificat ion, is used to exchange control and status information between the 73s1217f and the usb host. ? bulk in endpoint #1 ? bulk in endpoint #1 ? bulk out endpoint #1 ? bulk out endpoint #1 ? interrupt in endpoint #2 ? interrupt in endpoint #2 ? the usb block contains several fifos used for communication. ? the usb block contains several fifos used for communication. ? there is a 128-byte ram fifo for each bulk endpoi nt. maximum bulk packet size is 64 bytes. ? there is a 128-byte ram fifo for each bulk endpoi nt. maximum bulk packet size is 64 bytes. ? there is a 32-byte ram fifo for the interrupt endpoi nt. maximum interrupt packet size is 16 bytes. ? there is a 32-byte ram fifo for the interrupt endpoi nt. maximum interrupt packet size is 16 bytes. ? there is a 16-byte ram fifo for the control endpoi nt. maximum control packet size is 16 bytes. ? there is a 16-byte ram fifo for the control endpoi nt. maximum control packet size is 16 bytes. figure 15 shows the simplified block diagram of the usb interface. figure 15 shows the simplified block diagram of the usb interface. transceivers vdd 0 misctl1 d+ d- usb registers 16-byte fifo control endpoint 0 128-byte fifo bulk in endpoint 1 128-byte fifo bulk out endpoint 1 32-byte fifo interrupt in endpoint 2 48mhz clock usb full speed 12mbps serial interface engine 1 misctl1 usbpen usbcon figure 15: usb block diagram the usb interface consists of a serial interface engine (sie) t hat handles nrzi encoding/decoding, bit stuffing / unstuffing, and crc generation/checking. it also generates headers for packets to be transmitted and decodes the headers of received packets. an analog transceiver interfaces with the external usb bus. the usb inte rface hardware performs error checking and removes the usb protocol fields from the incoming messages before passing the data to the firmware. the hardware also adds the usb protocol fields to the outgoing messages comi ng from the firmware. the hardware implements nrzi encoding/decoding, crc checking/generation (bot h on data and token packets), device address downloaded from: http:///
73s1217f data sheet ds_1217f_002 decoding, handshake packet generation, data0/data1 t oggle synchronization, bit stuffing, bus idle detection and other protocol generation/checking requi red in chapter 8 of the usb specification. the firmware is responsible for servicing and build ing the messages required under chapter 9 of the usb specification. device configuration is stored in the firmware. data received from the usb port is stored in the appropriate in fifo that is read by the firmwa re and processed. the messages to be sent back to the usb host are generated by firmware and placed ba ck into the appropriate out fifo. stall/nak handshakes are generated as appropriate if the ram is not available for another message from the usb host. suspend and resume modes are supported. all r egister/fifo spaces are located in data memory space. the fifos are dedicated for usb storage and are unused in a configuration that is not using usb. all registers in the usb interface are lo cated in external data memory address (xram) space starting at address fc00h. 1.7.16.1 usb interface implementation the 73s1217f application programming interface includes some dedicated software commands to configure the usb interface, to get a status of eac h usb endpoint, to stall / unstall portions of the usb, and to send / receive data to / from each endpoint. usb api entirely manages the usb circ uitry, the usb registers and the fifos. use of those commands facilitates usb implementation, without dealing with low-level programming. miscellaneous control register 1 (misctl1): 0xfff2 ? 0x10 table 77: the misctl1 register msb lsb C C frpen flsh66 C anapen usbpen usbcon bit symbol function misctl1.7 C misctl1.6 C misctl1.5 frpen flash read pulse enable. misctl1.4 flsh66 flash read pulse. misctl1.3 C misctl1.2 anapen analog power enable. misctl1.1 usbpen 0 = enable the usb differential transceiver. misctl1.0 usbcon 1 = connect pull-up resistor from vdd to d+. if connected, the usb host will recognize the attachment of a usb device and begin enumeration. note: when using the usb on the 73s1217f, external 24 ? series resistors must be added to the d+ and d- signals to provide the proper impedance matching on these pins. the usb peripheral block is not able to support read or write operations to the usb sfr registers when the mpu clock is running at mpu clo ck rates of 12mhz or greater. in order to properly communicate with the usb sfr registers when running at these speeds, wait states must be inserted when addressing the usb sfrs. the ckcon register allows wait states to be inserted when accessing these registers. the proper settings for the number of wait states are shown in error! reference source not found. . when changing the mpu clock rate or the number of wait states, the usb connection must be inactive. if the usb is active, then it must be inactivated before changing the mpu clock or number of wait states. it can then be reconnected and re-enumerated. changing these parameters while the usb interface is active may cause communication errors on the usb interface. 76 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 77 clock control register (ckcon): 0x8e ? 0x01 table 78: the ckcon register msb lsb C C C C C ckwt.2 ckwt.1 ckwt.0 bit symbol function ckcon.7 C ckcon.6 C ckcon.5 C ckcon.4 C ckcon.3 C ckcon.2 ckwt.2 these three bits determine the number of wait states (machine cycles) to insert when accessing the usb sfrs: 000 = 0 (not to be used). 001 = 1 wait state. use when mpu clock is <12mhz. 010 = 2 wait states. use when mpu clock is between 12 and 16mhz. 011 = 3 wait states. use when mpu clock is 24mhz. 100 = 4 wait states. 101 = 5 wait states. 110 = 6 wait states. 111 = 7 wait states. ckcon.1 ckwt.1 ckcon.0 ckwt.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.17 smart card interface function the 73s1217f integrates one iso-7816 (t=0, t=1) uart, one complete icc electrical interface as well as an external smart card interface to allow mult iple smart cards to be connected using the teridian 73s8010x family of interface devices. figure 16 shows the simplified block diagram of the card circuitry (uart + interfaces), with deta il of dedicated xram registers. direct mode card insertion activation / deactivation sequencer vcc buffer / level shifter rst buffer / level shifter clk i/o buffer / level shifter c4 buffer / level shifter c8 buffer / level shifter vcc card generation icc event icc pwr_event i/o icc#1 i/oext. icc clk icc clkext. icc card clock management 7.2mhz scclk/ scsclk pres serial uart internal icc interface scsel uart t=0 t=1 rlength ststo atrmsb/lsb bgt/egt srxdata srxctl stxdata stxctl scprtcol scctl fdreg sbytectl sparctl card interrupt management scint scie external icc interface bypass mode xram registers vccctl/ vcctmr scclk/scsclk timers 2-byte tx fifo 2-byte rx fifo card and mode selection tx rx scdir scectl bgt0/1/2/3/ cwt0/1 sio sclk scclk scsclk figure 16: smart card interface block diagram card interrupts are managed through two dedicated registers scie (interrupt enable to define which interrupt is enabled) and scint (interrupt status). they allow the firmware to determine the source of an interrupt, that can be a card insertion / removal, card power fault, or a transmissi on (tx) or reception (rx) event / fault. it should be noted that even when card clock is disabled, an icc interrupt can be generated on a card insertion / removal to allow power saving modes. card insertion / removal is generated from the respective card switch detection inputs (whose polarity is programmable). 78 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 79 the built-in icc interface has a linear regulator (v cc generator) capable of drivi ng 1.8, 3.0 and 5.0v smart cards in accordance with the iso 7816-3 and emv4 .0 standards. this converter uses the v p (5.5v nominal) input supply source. see the power s upply management section above for more detail. auxiliary i/o lines c4 and c8 are only provided for the bu ilt-in interface. if support for the auxiliary lines is necessary for the external smart card interface, they need to be handled manually through the usr gpio pins. the external 73s8010x devices directly connec t the i/o (sio) and clock (sclk) signals and control is handled via the i 2 c interface. figure 17 shows how multiple 73s8010x devic es can be connected to the 73s1217f. 73s1217f 73s8010 73s8010 sc3 sc2 73s8010 sc(n) sc1 int3 sda scl int scl sda int scl sda int scl sda sad(0:2) sad(0:2) sad(0:2) i/o rst clk c4c8 vpc prespres pres iouc iouc iouc xtalin xtalin xtalin gnd pres vpc pres sio sclk vcc figure 17: smart card interface block diagram downloaded from: http:///
73s1217f data sheet ds_1217f_002 1.7.17.1 iso 7816 uart an embedded iso 7816 (hardware) uart is provided to control communications between a smart card and the 73s1217f mpu. the uart can be shared between the one built-in icc interface and the external icc interface. selection of the desired interface is made via the scsel register. control of the external interface is handled by the i 2 c interface for any external 73s8010x devices. the following is a list of features for the iso 7816 uart: ? two-byte fifo for temporary data storage on both tx and rx data. ? parity checking in t=0. this feature can be enabl ed/disabled by firmware. parity error reporting to firmware and break generation to icc can be controlled independently. ? parity error generation for test purposes. ? retransmission of last byte if icc indicates t=0 parity error. this feature can be enabled/disabled by firmware. ? deletion of last byte received if icc indicates t=0 parity error. this feature can be enabled/disabled by firmware. ? crc/lrc generation and checking. crc/lrc is automat ically inserted into t=1 data stream by the hardware. this feature can be enabled/disabled by firmware. ? support baud rates: 230000, 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware control (assuming 12mhz crystal) with various f/d settings. ? firmware manages f/d. all f/d combinations are supported in which f/d is directly divisible by 31 or 32 (i.e. f/d is a multiple of either 31 or 32). ? flexible etu clock generation and control. ? detection of convention (direct or indirect) characte r ts. this affects both polarity and order of bits in byte. convention can be overridden by firmware. ? supports wtx timeout with an expanded wait time counter (28 bits). ? a bypass mode is provided to bypass the hardware uart in order for the software to emulate the uart (for non-standard operating modes). in such a case, the i/o line value is reflected in sfr scctl or scectl respectively for the built-in or external in terfaces. this mode is appropriate for some synchronous and non t=0 / t=1 cards. the single integrated smart card uart is capabl e of supporting t=0 and t=1 cards in hardware, therefore offloading the bit manipulation tasks from the firmware. the embedded firmware instructs the hardware which smart card it should communicate with at any point in time. firmware reconfigures the uart as required when switching between smar t cards. when the 73s1217f has transmitted a message with an expected response, the firmware s hould not switch the uart to another smart card until the first smart card has responded. if the smart card responds while another smart card is selected, that first smart cards response will be ignored. 80 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 81 1.7.17.2 answer to reset processing a card insertion event generates an interrupt to the firmware, which is then responsible for the configuration of the electrical interface, the uart and activation of the card. the activation sequencer goes through the power up sequence as defined in the iso 7816-3 specification. an asynchronous activation timing diagram is shown in figure 18 . after the card rst is de-asserted, the firmware instructs the hardware to look for a ts byte that begins the at r response. if a response is not provided within the pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instructing the 73s1217f to begi n a deactivation sequence. once commanded, the deactivation sequencer goes through the power down sequence as defined in the iso 7816-3 specification. if an atr response is received, t he hardware looks for a ts byte that determines direct/inverse convention. the hardware handles t he indirect convention c onversion such that the embedded firmware only receives direct convention. th is feature can be disabled by firmware within the sbytectl register. parity checking and break generation is performed on the ts byte unless disabled by firmware. if during the card session, a card removal, over-current or other erro r event is detected, the hardware will automatically perform the deactiva tion sequence and then generate an interrupt to the firmware. the firmware can then perform any other error handling required for proper system operation. smart card rst, i/o and clk, c4, c8 shall be low before the end of the deactivation sequence. figure 19 shows the timing for a deactivation sequence. vccsel bits vcc vccok bit rstcrd bit rst clk io t1 t2 t3 t4 t5 tto see note atr starts t4 selsc bits t1: selsc.1 bit set (selec ts internal icc interface) and a non-zero value in vccsel bits (calling for a value of vcc of 1.8, 3.0, or 5.0 volts) will begin t he activation sequence. t1 is the time for vcc to rise to acceptable level, declared as vcc ok (bit vcco k gets set). this time depends on filter capacitor value and card icc load. tto: the time allowed for vcc to rise to vcc ok stat us after setting of the vccsel bits. this time is generated by the vcctmr counter. if vcc ok is not set, (bit vccok) at this time, a deactivation will be initiated. vccsel bits are not automatically cl eared. the firmware must clear the vccsel bits before starting a new activation. t2: time from vcctmr timeout and vcc ok to io reception (high), typically 2-3 clk cycles if rdyst = 0. if rdyst = 1, t2 starts when vccok = 1. t3: time from io = high to clk start, typically 2-3 clk cycles. t4: time allowed for start of clk to de- assertion of rst. programmable by the rlength register. t5: time allowed for atr timeout, set by the ststo register. note: if the rstcrd bit is set, rst is assert ed (low). upon clearing rstcrd bit, rst will be de-asserted after t4. figure 18: asynchronous activation sequence timing downloaded from: http:///
73s1217f data sheet ds_1217f_002 82 rev. 1.2 vcc io rst clk t1 t2 t3 t4 t5 firmware sets vccsel to 00 cmdvccnb t5 delay or card event t1: time after either a card event occurs or fi rmware sets the vccsela and vccselb bits to 0 (see t5, vccoff_tmr) occurs until rst is asserted low. t2: time after rst goes low until clk stops. t3: time after clk stops until io goes low. t4: time after io goes low until vcc is powered down. t5: delayed vcc off time (in etus per vccoff_tmr bits). only in effect due to firmware deactivation. figure 19: deactivation sequence 1.7.17.3 data reception/transmission when a 12mhz crystal is used, the smart card uart will generate a 3.69mhz (default) clock to both smart card interfaces. this will allow approxim ately 9600bps (1/etu) communication during atr (iso 7816 default) . as part of the pps negotiation between the smart card and the reader, the firmware may determine that the smart card parameters f and d ma y be changed. after this negotiation, the firmware may change the etu by writing to the sfr fdreg to adjust the etu and clk. the firmware may also change the smart card clock frequency by writing to the sfr scclk ( sceclk for external interface). independent clock frequency control is provided to each sm art card interface. clock stop high or clock stop low is supported in asynchronous mode. figure 20 shows the etu and clk control circuits. the firmware determines when clock stop is supported by t he smart card and when it is appropriate to go into that mode (and when to come out of it). the smart ca rd uart is clocked by the same clock is provided to the selected smart card. the transition between sm art card clocks is handled in hardware to eliminate any glitches for the uart during switchover. t he external smart card clock is not affected when switching the uart to communicate with the internal smart card. downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 83 pll etu divider 12 bits fi decoder div by 2 etuclk clk div by 2 sclk pre-scaler 6 bits pre-scaler 6 bits f/d register scclk(5:0) scsclk(5:0) msclk msclke mclk = 96mhz fdreg(3:0) fdreg(7:4) 9926 1/744 3.69m 1/13 7.38m 7.38m 3.69m 7.38m defaults in italics scsel(3:2) 1/13 sync center edge figure 20: smart card clk and etu generation there are two, two-byte fifos that are used to buffer transmit and receive data. during a t=0 processing, if a parity error is detected by the 73s1217f during message reception, an error signal (break) will be generated to the smart card. the byte received will be discarded and the firmware notified of the error. break generation and receive byte dropping can be disabled under firmware control. during the transmission of a byte, if an error signal (break) is detected, the last byte is retransmitted again and the firmware notified. retransmission can be disabled by firmware. when a correct byte is received, an interrupt is generated to the firmware, which then reads the byte from the receive fifo. receive overruns are detected by the hardware and reported via an interr upt. during transmission of a message, the firmware will write bytes into the transmit fifo . the hardware will send them to the smart card. when the last byte of a message has been written, the firmware will need to set the lasttx bit in the stxctl sfr. this will cause the hardware to insert the crc/lrc if in a t=1 protocol mode. crc/lrc generation/checking is only provided during t=1 processing. firmware will need to instruct the smart function to go into receive mode after this last transmit data byte if it expects a response from the smart card. at the end of the smart card response, the firmware will put the interface back into transmit mode if appropriate. the hardware can check for the following card-related timeouts: ? character waiting time (cwt). ? block waiting time (bwt). ? initial waiting time (iwt). the firmware will load the wait time registers with the appropriate value for the operating mode at the appropriate time. figure 21 shows the guard, block, wait and atr time definitions. if a timeout occurs, an interrupt will be generated and the firmware can take appropriate recovery steps. support is provided for adding additional guard times between characters using the extra guard time register (egt) and between the last byte received by the 73s1217f and the first byte tr ansmitted by the 73s1217f using the block guard time register (bgt) . other than the protocol checks described above, the firmware is responsible for all protocol checking and error recovery. downloaded from: http:///
73s1217f data sheet ds_1217f_002 > egt < wwt char 1 char 2 char n+1 char n+2 char n+3 block1 block2 > bwt < cwt reception transmission t = 1 mode char 1 char 2 char n rst tsto(7:0) atrto(15:0) vcc_ok rlen(7:0) char 1 char 2 char n atr timing parameters iwt(15:0) bgt(4:0) tx t = 0 mode io egt (by seting last_txbyte and tx/rxb=0 during char n, rx mode will start after last tx byte) wwt is set by the value in the bwt registers. figure 21: guard, block, wait and atr time definitions 1.7.17.4 bypass mode it is possible to bypass the smart card uart in order for the firmware to support non-t=0/t=1 smart cards. this is called bypass mode. in this m ode the embedded firmware will communicate directly with the selected smart card and drive i/o during transmit and read i/o during receive in order to communicate with the smart card. in this mode, atr processi ng is under firmware control. the firmware must sequence the interface signals as required. firmware must perform ts processing, parity checking, break generation and crc/lrc calculation (if required). 1.7.17.5 synchronous operation mode the 73s1217f supports synchronous operation. when sync mode is selected for either interface, the clk signal is generated by the etu counter. the values in fdreg , scclk , and sceclk must be set to obtain the desired sync clk rate. there is only one etu counter and therefore, in sync mode, the interface must be selected to obtain a smart card cl ock signal. in sync mode, input data is sampled on the rise of clk, and output dat a is changed on the fall of clk. special notes regarding synchronous mode operation 84 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 85 when the scisyn or scesnc bits ( sprtcol , bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there ar e changes in the definition and behavior of pertinent register bits and associated circuitry. the following requirements are to be noted: 1. the source for the smart card clock (clk or sc lk) is the etu counter. only the actively selected interface can have a running synchronous clock. in contrast, an unselected interface may have a running clock in the asynchronous mode of operation. 2. the control bits clklvl, sclklvl, clkoff, and sclkoff are functional in synchronous mode. when the clkoff bit is set, it will not truncate either the logic low or logic high period when the (stop at) level is of opposite polarity. the clk/sclk si gnal will complete a correct logic low or logic high duty cycle before stopping at the sele cted level. the clk start is a result of the falling edge of the clkoff bit. setting clock to run when it is stopped low will result in a half period of low before going high. setting clock to run when it is stopped high will result in the clock going low immediately and then running at the selected rate with 50% duty cycle (within the limitations of the etu divisor value). 3. the rlen(7:0) is configured to count the falling edges of the etu clock (clk or sclk) after it has been loaded with a value from 1 to 255. a value of 0 disables the counting function and rlen functions such as i/o source selection (i/o signal bypasses the fifos and is controlled by the scclk / sceclk sfrs). when the rlen counter reaches the max (loaded) value, it sets the waitto interrupt ( scint , bit 7), which is maskable via wtoien ( scie , bit 7). i2cmode it must be reloaded in order to start the counting/clocking process again. this allows the processor to select the number of clk cycles and hence, the number of bi ts to be read or written to/from the card. 4. the fifo is not clocked by the first clk (falli ng) edge resulting from a clkoff de-assertion (a clock start event) when the clk was stopped in the high state and rlen has been loaded but not yet clocked. 5. the state of the pin io or sio is sampled on the rising edge of clk/sclk and stored in bit 5 of the scctl / scectl register. 6. when rlen = max or 0 and i2cmode = 1 ( stxctl , b7), the io or sio signal is directly controlled by the data and direction bits in the respective scctl and scectl register. the state of the data in the tx fifo is bypassed. 7. in the sprtcol register, bit 6 (mode9/8b) becomes acti ve. when set, the rxdata fifo will read nine-bit words with the state of the ninth bit being readable in srxctl , bit 7 (b9dat). the rxdav interrupt will occur when the ninth bit has been clocked in (rising edge of clk or sclk). 8. care must be taken to clear the rx and tx fifos at the start of any transacti on. the user shall read the rx fifo until it indicates empty status. r eading the tx fifo twice will reset the input byte pointer and the next write to the tx fifo will load the by te to the first out position. note that the bit pointer (serializer/deserializer) is reset to bit 0 on any change of the tx/rxd bit. special bits that are only active for sync mode include: srxctl , b7 bit9dat, sprtcol b6 mode9/8b, stxctl , b7 i2cmode, and the definition of scint b7, which was waitto, becomes rlenint interrupt, and scie b7, which was wtoien, becomes rlenien. downloaded from: http:///
73s1217f data sheet ds_1217f_002 vcc vccok rstcrd rst clk io t1 t2 t3 t4 tto vccsel bits t1: the time from setting vccsel bits until vccok = 1. tto: the time from setting vccsel bits until vcctmr time s out. at t1 (if rdyst = 1) or tto (if rdyst = 0), activation starts. it is suggested to have rdyst = 0 and use the vcctmr interrupt to let mpu know when sequence is starting. t2: time from start of activation ( no external indication) until io goes into reception mode (= 1). this is approximately 4 scclk (or sceclk ) clock cycles. t3: minimum one half of etu period. t4: etu period. note that in sync mode, io as input is sampled on the rising edge of clk. io changes on the falling edge of clk, either from the card or from the 73s1217f. the rst signal to the card is directly controlled by the rstcrd bit (non-inverted) via the mpu and is s hown as an example of a possible rst pattern. figure 22: synchronous activation io reception on rst clk clkoff clklvl rlength interrupt rlength count rlenght = 1 tx/rxb mode bit (tx = '1') 1. clear clkoff after card is in reception mode. 2. set rst bit. 3. interrupt is generated when rlength counter is max. 4. read and clear interrupt. 5. clear rst bit. 6. toggle tx/rxb to reset bit counter. 7. reload rlength counter. count max 1 2 4 7 5 t1. clk wll start at least 1/2 etu after clkoff is set low when clklvl = 0 t1 3 6 figure 23: example of sync mode oper ation: generating/reading atr signals 86 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 87 rlength count - was set for length of atr clk io rlength interrupt clk stop clk stop level io bit iodir bit tx/rx mode bit tx = '1' data from card -end of atr data from tx fifo rlength count max 1. interrupt generated when rlength counter is max. 2. read and clear interrupt. 3. set clk stop and clk stop level high in interrupt routine. 4. set tx/rx bit to tx mode. 5. reload rlength counter. 6. set io bit low and iodir = output. since rlen=(max or 0) and tx/rx =1, io pin is controlled by io bit. 7. clear clk stop and clk stop level. note: data in tx fifo should not be empty here. start bit synchronous clock start/stop mode style start bit procedure. this procedure should be used to generate the start bit insertion in synchronous mode for synchronous clock start/stop mode protocol. rlen=0 rlen=1 2 1 3 7 6 5 6 4 figure 24: creation of synchronous clock start/stop mode start bit in sync mode rlength count (rlength = 9) clk io rlength interrupt clk stop clk stop level io bit iodir bit tx/rx mode bit tx = '1' i2cmode = 1: data to/from card i2cmode = 0: data from tx fifo i2cmode = 1:ack bit (to/from card) i2cmode = 0: data from tx fifo rlength count max 1. interrupt generated when rlength counter is max. 2. read and clear interrupt. 3. set clk stop and clk stop level high, set io bit low and iodir = output. 4. set io bit high and iodir = output. 5. set tx/rx bit to rx mode. 6. reload rlength counter. 7. clear clk stop and clk stop level. stop bit synchronous clock start/stop mode stop bit procedure. this procedure should be used to generate the stop bit in synchronous mode. 1 2 4 3 5 7 6 min ? etu figure 25: creation of synchronous clock start/stop mode stop bit in sync mode downloaded from: http:///
73s1217f data sheet ds_1217f_002 rlength count rlength = 9 clk io rlength interrupt rx data tx/rx mode bit tx = '1' data from card (bit 8) data from card (bit 1) rlength count max rlen=9 protection bit (bit 9) rx fifo (data from card is ready for cpu read) protection bit is ready for cpu read rlen=8 rlen=0 rlen =1 protection bit data (bit 9) 1._ interrupt generated when rlength counter is max 2._ read and clear interrupt 3._ reload rlength counter rlength count rlength = 9 rlength count max rlen=9 rlen=8 rlength interrupt clk clk stop clk stop level = 0 1._ interrupt generated when rlength counter is max 2._stop clk after the last byte and protection bit stop clk after receiving the last byte and protection bit. receive data in 9 bit mode figure 26: operation of 9-bit mode in sync mode synchronous card operation is broken down into three primary types. t hese are commonly referred to as 2-wire, 3-wire and i2c synchronous cards. each card type requires different control and timing and therefore requires different algorithms to access. teridian has created an application note to provide detailed algorithms for each card type. refer to the application note titled 73s12xxf synchronous card design application note . 88 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 89 1.7.17.6 smart card sfrs smart card select register (scsel): 0xfe00 ? 0x00 the smart card select register is used to determine which smart card interface is using the iso uart. the internal smart card has integrated 7816-3 compliant sequencer circuitry to drive an external smart card interface. the external smart card inte rface relies on 73s8010x parts to generate the iso 7816-3 compatible signals and sequences. multiple 73s8010x devices can be connected to the external smart card interface. table 79: the scsel register msb lsb C C C C selsc.1 selsc.0 bypass C bit symbol function scsel.7 C scsel.6 C scsel.5 C scsel.4 C scsel.3 selsc.1 select smart card interface C these bits select the interface that is using the is0 uart. these bits do not acti vate the interface. activation is performed by the vccctl register. 00 = no smart card interface selected. 01 01 = external smart card interface selected (using sclk, sio). 02 1x = internal smart card interface selected. scsel.2 selsc.0 scsel.1 bypass 1 = enabled, 0 = disabled. when enabl ed, iso uart is bypassed and the i/o line is controlled via the scctl and scectl registers. scsel.0 C downloaded from: http:///
73s1217f data sheet ds_1217f_002 smart card interrupt register (scint): 0xfe01 ? 0x00 when the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. the bits ar e cleared when this register is read. each interrupt can be disabled by the smart card interrupt enable register. error processing must be handled by the firmware. this register relates to the interface that is active C see the scsel register (above). table 80: the scint register msb lsb waitto crdevt vcctmri rxdav txevt txsent txerr rxerr bit symbol function scint.7 waitto wait timeout C an atr or card wait timeout has occurred. in sync mode, this interrupt is asserted when the rlen counter (it advances on falling edges of clk/etu) reaches the loaded (max) value. this bit is cleared when the scint register is read. when running in synchronous clock stop mode, this bit becomes r lenint interrupt (set when the rlen counter reaches the terminal count). scint.6 crdevt card event C a card event is signal ed via pin detcard either when the card was inserted or removed (read the crdctl register to determine card presence) or there was a fault c ondition in the interface circuitry. this bit is functional even if the smart card logic clock is disabled and when the pwrdn bit is set. this bit is cleared when the scint register is read. scint.5 vcctmri vcc timer C this bit is set when the vcctmr times out. this bit is cleared when the scint register is read. scint.4 rxdav rx data available C data was received from the smart card because the rx fifo is not empty. in bypass mode, this interrupt is generated on a falling edge of the smart card i/o line. after receiving this interrupt in bypass mode, firmware should disable it until the firmware has received the entire byte and is waiting for the next start delimiter. this bit is cleared when there is no rx data available in the rx fifo. scint.3 txevnt tx event C set whenever the txemty or txfull bits are set in the srxctl sfr. this bit is cleared when the stxctl register is read. scint.2 txsent tx sent C set whenever the iso ua rt has successfully transmitted a byte to the smart card. also set when a crc/lrc byte is sent in t=1 mode. will not be set in t=0 when a break is detected at the end of a byte (when break detection is enabled) . this bit is cleared when the scint register is read. scint.1 txerr tx error C an error was detected dur ing the transmission of data to the smart card as indicated by either breakd or txundr bit being set in the stxctl sfr. additional information can be found in that register description. this bit is cleared when the stxctl register is read. scint.0 rxerr rx error C an error was detected dur ing the reception of data from the smart card. additional information can be found in the srxctl register. this interrupt will be asserted for rxov rr, or rx parity error events. this bit is cleared when the srxctl register is read. 90 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 91 smart card interrupt enable register (scie): 0xfe02 ? 0x00 when set to 1, the respective condition can cause a smar t card interrupt. when set to a 0, the respective condition cannot cause an interrupt. when disabled, t he respective bit in the smart card interrupt register can still be set, but it will not interrupt the mpu. table 81: the scie register msb lsb wtoien cdeven vtmren rxdaen txeven txsnten t xeren rxeren bit symbol function scie.7 wtoien wait timeout interrupt enable C enable for atr or wait timeout interrupt. in sync mode, function is rlie n (rlen = max.) interrupt enable. scie.6 cdeven card event interrupt enable. scie.5 vtmren vcc timer interrupt enable. scie.4 rxdaen rx data available interrupt enable. scie.3 txeven tx event interrupt enable. scie.2 txsnten tx sent interrupt enable. scie.1 txeren tx error interrupt enable. scie.0 rxeren rx error interrupt enable. downloaded from: http:///
73s1217f data sheet ds_1217f_002 smart card v cc control/status register (vccctl): 0xfe03 ? 0x00 this register is used to control t he power up and power down of the integr ated smart card interface. it is used to determine whether to apply 5v, 3v, or 1.8v to the smart card. perform the voltage selection with one write operation, setting both vccsel.1 and vccsel .0 bits simultaneously. the vddflt bit (if enabled) will provide an emergency deactivation of the internal smart card slot. see the vdd fault detect function section for more detail. table 82: the vccctl register msb lsb vccsel.1 vccsel.0 vddflt rdyst vccok C C scpwrdn bit symbol function vccctl.7 vccsel.1 setting non-zero value for bits 7,6 will begin activation sequence with target vcc as given below: state vccsel.1 vccsel.0 vcc 1 0 0 0v 2 0 1 1.8v 3 1 0 3.0v 4 1 1 5v a card event or vccok going low will initiate a deactivation sequence. when the deactivation sequence for rst, clk and i/o is complete, v cc will be turned off. when this type of deactiva tion occurs, the bits must be reset before initiating another activation. vccctl.6 vccsel.0 vccctl.5 vddflt if this bit is set = 0, the cmdvcc3b and cmdvcc5b outputs are immediately set = 1 to signal to the companion circuit to begin deactivation when there is a vdd fault event. if th is bit is set = 1 and there is a vdd fault, the firmware should perform a deactivation sequence and then set cmdvcc3b or cmdvcc5b = 1 to signal the companion circuit to set vcc = 0. vccctl.4 rdyst if this bit is set = 1, the activati on sequence will start when bit vccok is set = 1. if not set, the deactivation sequence shall start when the vcctmr times out. vccctl.3 vccok (read only). indicates that v cc output voltage is stable. vccctl.2 C vccctl.1 C vccctl.0 scpwrdn this bit controls the power-off mode of the 73s1217f circuit. 1 = power off, 0 = normal operation. when in power down mode, v dd = 0v. v dd can only be turned on by pressing the on/off switch or by application of 5v to v bus . if v bus power is available and scpwrdn bit is set, it has no effect until v bus is removed and v dd will shut off. 92 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 93 v cc stable timer register (vcctmr): 0xfe04 ? 0x0f a programmable timer is provided to set the time from activation start (setting the vccsel.1 and vccsel.0 bits to non-zero) to when vcc_ok is ev aluated. vcc_ok must be true at the end of this timers programmed interval (tto in figure 18 ) in order for the activation sequence to continue. if vcc_ok is not true and the end of the interval (tto), t he card event interrupt will be set, and a deactivation sequence shall begin including clearing of the vccsel bits. table 83: the vcctmr register msb lsb offtmr.3 offtmr.2 offtmr.1 offtmr.0 v cctmr.3 vcctmr.2 vcctmr.1 vcctmr.0 bit symbol function vcctmr.7 offtmr.3 vcc off timer C the bits set the delay (in number of etus) for deactivation after the vccsel.1 and vcc sel.0 have been set to 0. the time value is a count of the 32768hz clock and is given by tto = offtmr(7:4) * 30.5 s. this delay does not affect emergency deactivations due to vdd fault or card events. a value of 0000 results in no additional delay. vcctmr.6 offtmr.2 vcctmr.5 offtmr.1 vcctmr.4 offtmr.0 vcctmr.3 vcctmr.3 vcc timer C vccok must be true at t he time set by the value in these bits in order for the activation sequenc e to continue. if not, the vccsel bits will be cleared. the time value is a count of the 32768hz clock and is given by tto = vcctmr(3:0) * 30.5 s. a value of 0000 results in no timeout, not zero time, and activation requires that rdyst is set and rdy goes high. vcctmr.2 vcctmr.2 vcctmr.1 vcctmr.1 vcctmr.0 vcctmr.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 card status/control register (crdctl): 0xfe05 ? 0x00 this register is used to configure the card detect pin (detcard) and monitor card detect status. this register must be written to properly configure d ebounce, detect_polarity (= 0 or = 1), and the pull- up/down enable before setting cdeten. the card detect l ogic is functional even without smart card logic clock. when the pwrdn bit is set = 1, no debounc e is provided but card presence is operable. table 84: the crdctl register msb lsb debou n cdeten C C detpol puenb pden cardin bit symbol function crdctl.7 deboun debounce C when set = 1, this will enable hardware de-bounce of the card detect pin. the de-bounce function shall wait for 64ms of stable card detect asse rtion before setting the cardin bit. this counter/timer uses t he keypad clock as a source of 1khz signal. de-assertion of the cardin bit is immediate upon de-assertion of the card detect pin(s). crdctl.6 cdeten card detect enable C when set = 1, activates card detection input. default upon power-on reset is 0. crdctl.5 C crdctl.4 C crdctl.3 detpol detect polarity C when set = 1, the detcard pin shall interpret a logic 1 as card present. crdctl.2 puenb enable pull-up current on detcard pin (active low). crdctl.1 pden enable pull-down current on detcard pin. crdctl.0 cardin card inserted C (read only). 1 = card inserted, 0 = card not inserted. a change in the value of this bit is a card event. a read of this bit indicates whether smart card is inserted or not inserted in conjunction with the detpol setting. 94 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 95 tx control/status register (stxctl): 0xfe06 ? 0x00 this register is used to control tr ansmission of data to the smart card. some control and some status bits are in this register. table 85: the stxctl register msb lsb i2cmode C txfull txemty txundr lasttx tx/rxb breakd bit symbol function stxctl.7 i2cmode i2c mode C when in sync mode and this bit is set, and when the rlen count value = max or 0, the source of the smart card data for io pin (or sio pin) will be connected to the io bit in scctl (or scectl) register rather than the tx fifo. see the description for the protocol mode register for more detail. stxctl.6 C stxctl.5 txfull tx fifo is full. additional writes may corrupt the contents of the fifo. this bit it will remain set as long as the tx fifo is full. generates a tx_event interrupt upon going full. stxctl.4 txemty 1 = tx fifo is empty, 0 = tx fifo is not empty. if there is data in the tx fifo, the circuit will transmit it to the smart card if in transmit mode. in t=1 mode, if the lasttx bit is set and the hardware is configured to transmit the crc/lrc, the txemty will not be set unt il the crc/lrc is transmitted. in t=0, if the lasttx bit is set, txemty will be set after the last word has been successfully transmitted to the smart card. generates a txevnt interrupt upon going empty. stxctl.3 txundr tx underrrun C (read only) asserted when a transmit under-run condition has occurred. an under-run condition is defined as an empty tx fifo when the last data word has been successfully transmitted to the smart card and the lasttx bit was not set. no s pecial processing is performed by the hardware if this condition occurs. cl eared when read by firmware. this bit generates a txerr interrupt. stxctl.2 lasttx last tx byte C set by firmware (in bot h t=0 and t=1) when the last byte in the current message has been written into the transmit fifo. in t=1 mode, the crc/lrc will be appended to the message. should be set after the last byte has been written into the transmit fifo. should be cleared by firmware before writing first byte of next message into the transmit fifo. used in t=0 to determine when to set txemty. stxctl.1 tx/rxb 1 = transmit mode, 0 = receive mode. configures the hardware to be receiving from or transmitting to the sm art card. determines which counters should be enabled. this bit should be set to receive mode prior to switching to another interface. setting and rese tting this bit shall initialize the crc logic. if lasttx is set, this bit can be reset to rx mode and uart logic will automatically change mode to rx when tx operation is completed (tx_empty =1). stxctl.0 breakd break detected C (read only) 1 = a break has been detected on the i/o line indicating that the smart card detect ed a parity error. cleared when read. this bit generates a txerr interrupt. downloaded from: http:///
73s1217f data sheet ds_1217f_002 stx data register (stxdata): 0xfe07 ? 0x00 table 86: the stxdata register msb lsb stxdat.7 stxdat.6 stxdat .5 stxdat.4 stxdat.3 stxd at.2 stxdat.1 stxdat.0 bit function stxdata.7 data to be transmitted to smart card. gets stored in the tx fifo and then extracted by the hardware and sent to the selected smart card. when the mpu reads this register, the byte pointer is changed to effectively read out the data. thus, two reads will always result in an empty fifo condition. the contents of the fi fo registers are not cleared, but will be overwritten by writes. stxdata.6 stxdata.5 stxdata.4 stxdata.3 stxdata.2 stxdata.1 stxdata.0 96 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 97 srx control/status register (srxctl): 0xfe08 ? 0x00 this register is used to monitor re ception of data from the smart card. table 87: the srxctl register msb lsb bit9dat C lastrx crcerr rxfull rxemty rxovr r paritye bit symbol function srxctl.7 bit9dat bit 9 data C when in sync mode and with mode9/8b set, this bit will contain the data on io (or sio) pin that wa s sampled on the ninth clk (or sclk) rising edge. this is used to read data in synchronous 9-bit formats. srxctl.6 C srxctl.5 lastrx last rx byte C user sets this bit during the reception of the last byte. when byte is received and this bit is set, logic checks crc to match 0x1d0f (t=1 mode) or lrc to match 00h (t=1 mode), otherwise a crc or lrc error is asserted. srxctl.4 crcerr (read only) 1 = crc (or lrc) error has been detected. srxctl.3 rxfull (read only) rx fifo is full. status bit to indicate rx fifo is full. srxctl.2 rxemty (read only) rx fifo is empty. th is is only a status bit and does not generate an rx interrupt. srxctl.1 rxovrr rx overrun C (read only) asserted w hen a receive-over-run condition has occurred. an over-run is defined as a byte was received from the smart card when the rx fifo was full. invalid data may be in the receive fifo. firmware should take appropriate action. cleared when read. additional writes to the rx fifo are disca rded when a rxovrr occurs until the overrun condition is cleared. will generate an rxerr interrupt. srxctl.0 paritye parity error C (read only) 1 = the l ogic detected a parity error on incoming data from the smart card. cleared when read. will generate rxerr interrupt. downloaded from: http:///
73s1217f data sheet ds_1217f_002 srx data register (srxdata): 0xfe09 ? 0x00 table 88: the srxdata register msb lsb srxdat.7 srxdat.6 srxdat.5 srxdat.4 srxdat.3 srxdat.2 sr xdat.1 srxdat.0 bit function srxdata.7 (read only) data received from the smart card. data received from the smart card gets stored in a fifo that is read by the firmware. srxdata.6 srxdata.5 srxdata.4 srxdata.3 srxdata.2 srxdata.1 srxdata.0 98 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 99 smart card control register (scctl): 0xfe0a ? 0x21 this register is used to monitor re ception of data from the smart card. table 89: the scctl register msb lsb rstcrd C io iod c8 c4 clklvl clkoff bit symbol function scctl.7 rstcrd 1 = asserts the rst (set rst = 0) to the smart card interface, 0 = de- assert the rst (set rst = 1) to the smart card interface. can be used to extend rst to the smart card. refer to the rlength register description. this bit is operational in all modes and can be used to extend rst during activation or perform a warm reset as required. in auto-sequence mode, this bit should be set = 0 to allow the sequencer to de-assert rst per the rlength parameters. in sync mode (see the sprtcol register) the sense of this bit is non-inverted, if set =1 , rst = 1, if set = 0, rst = 0. rlen has no effect on reset in sync mode. scctl.6 C scctl.5 io smart card i/o. read is state of i/o signal (caution, this signal is not synchronized to the mpu clock). in bypass mode, write value is state of signal on i/o. in sync mode, this bit will contain the value of i/o pin on the latest rising edge of clk. scctl.4 iod smart card i/o direction control by pass mode or sync mode. 1 = input (default), 0 = output. scctl.3 c8 smart card c8. when c8 is an output, the value written to this bit will appear on the c8 line. the value read when c8 is an output is the value stored in the register. when c8 is an input, the value read is the value on the c8 pin (caution, this signal is not synchronized to the mpu clock). when c8 is an input, the value written will be stored in the register but not presented to the c8 pin. scctl.2 c4 smart card c4. when c4 is an output, the value written to this bit will appear on the c4 line. the value read when c4 is an output is the value stored in the register. when c4 is an input, the value read is the value on the c4 pin (caution, this signal is not synchronized to the mpu clock). when c4 is an input, the value written will be stored in the register but not presented to the c4 pin. scctl.1 clklvl 1 = high, 0 = low. if clkoff is set = 1, the clk to smart card will be at the logic level indicated by this bit. if in bypass mode, this bit directly controls the state of clk. scctl.0 clkoff 0 = clk is enabled. 1 = clk is not enabled. when asserted, the clk will stop at the level selected by clklvl. this bit has no effect if in bypass mode. downloaded from: http:///
73s1217f data sheet ds_1217f_002 external smart card control register (scectl): 0xfe0b ? 0x00 this register is used to directly set and sample signals of external smart card interface. there are three modes of asynchronous operation, an automatic sequence mode, and bypass mode. clock stop per the iso 7816-3 interface is also supported but firmwa re must handle the protocol for sio and sclk for i 2 c clock stop and start. control for reset (to make rs t signal), activation control, voltage select, etc. should be handled via the i 2 c interface when using external 73s73s 8010x devices. usr(n) pins shall be used for c4, c8 functions if necessary. table 90: the scectl register msb lsb C C sio siod C C sclklvl sclkoff bit symbol function scectl.7 C scectl.6 C scectl.5 sio external smart card i/o. bit when read indicates state of pin sio for siod = 1 (caution, this signal is not synchronized to the mpu clock), when written, sets the state of pin sio for siod = 0. ignored if not in bypass or sync modes. in sync mode, this bit will contain the value of io pin on the latest rising edge of sclk. scectl.4 siod 1 = input, 0 = output. external smart card i/o direction control. ignored if not in bypass or sync modes. scectl.3 C scectl.2 C scectl.1 sclklvl sets the state of sclk when disabled by sclkoff bit. if in bypass mode, this bit directly controls the state of sclk. scectl.0 sclkoff 0 = sclk enabled, 1 = sclk disabled. when disabled, sclk level is determined by sclklvl. this bit has no effect if in bypass mode. 100 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 101 c4/c8 data direction register (scdir): 0xfe0c ? 0x00 this register determines the direction of the internal interface c4/c8 lines. after reset, all signals are tri-stated. table 91: the scdir register msb lsb C C C C c8d c4d C C bit symbol function scdir.7 C scdir.6 C scdir.5 C scdir.4 C scdir.3 c8d 1 = input, 0 = output. smart card c8 direction. scdir.2 c4d 1 = input, 0 = output. smart card c4 direction. scdir.1 C scdir.0 C downloaded from: http:///
73s1217f data sheet ds_1217f_002 protocol mode register (sprtcol): 0xfe0d ? 0x03 this register determines the protocol to be use when communicating with the selected smart card. this register should be updated as required when sw itching between smart card interfaces. table 92: the sprtcol register msb lsb scisyn mod9/8b scesyn 0 tmode crcen crcms rcvatr bit symbol function sprtcol.7 scisyn smart card internal synchronous mode C configures internal smart card interface for synchronous mode. this mode routes the internal interface buffers for rst, io, c4, c8 to scctl register bits for direct firmware control. clk is generated by the etu counter. sprtcol.6 mod9/8b synchronous 8/9 bit mode select C for sy nc mode, in protocols with 9-bit words, set this bit. the first eight bits read go into the rx fifo and the ninth bit read will be stored in the io (or sio) data bit of the srxctl register. sprtcol.5 scesyn smart card external synchronous mode C configures external smart card interface for synchronous mode. this mode routes the external smart card interface buffers for sio to scectl register bits for direct firmware control. sclk is generated by the etu counter. sprtcol.4 0 reserved bit, must always be set to 0. sprtcol.3 tmode protocol mode select C 0: t=0, 1: t=1. determines which smart card protocol is to be used during message processing. sprtcol.2 crcen crc enable C 1 = enabled, 0 = disabled. enables the checking/generation of crc/lrc while in t=1 mode. has no effect in t=0 mode. if enabled and a message is being transmitted to the smart card, the crc/lrc will be inserted into the message stream after the last tx byte is transmitted to the smart ca rd. if enabled, crc/lrc will be checked on incoming messages and the value made available to the firmware via the crc ls/ms registers. sprtcol.1 crcms crc mode select C 1 = crc, 0 = lrc. determines type of checking algorithm to be used. sprtcol.0 rcvatr receive atr C 1 = enable atr timeout, 0 = disable atr timeout. set by firmware after the smart card has been turned on and the hardware is expecting atr. 102 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 103 sc clock configuration register (scclk): 0xfe0f ? 0x0c this register controls the internal smart card (clk) clock generation. table 93: the scclk register msb lsb C C iclkfs.5 iclkfs.4 iclkfs.3 iclkfs.2 iclkfs.1 iclkfs.0 bit symbol function scclk.7 C scclk.6 C scclk.5 iclkfs.5 internal smart card clk frequency sele ct C division factor to determine internal smart card clk frequency. mclk clock is divided by (register value + 1) to clock the etu divider, and then by 2 to generate clk. default ratio is 13. the programmed value in th is register is applied to the divider after this value is written, in such a manner as to produce a glitch-free output, regardless of the selection of acti ve interface. a register value = 0 will default to the same effect as register value = 1. scclk.4 iclkfs.4 scclk.3 iclkfs.3 scclk.2 iclkfs.2 scclk.1 iclkfs.1 scclk.0 iclkfs.0 external sc clock configurat ion register (sceclk): 0xfe10 ? 0x0c this register controls the external smart card (sclk) clock generation. table 94: the sceclk register msb lsb C C eclkfs.5 eclkfs.4 eclkfs. 3 eclkfs.2 eclkfs.1 eclkfs.0 bit symbol function sceclk.7 C sceclk.6 C sceclk.5 eclkfs.5 external smart card clk frequency sele ct C division factor to determine external smart card clk frequency. mclk clock is divided by (register value + 1) to clock the etu divider, and then by 2 to generate sclk. default ratio is 13. the programmed value in this register is applied to the divider after this value is written, in such a manner as to produce a glitch- free output, regardless of the selection of active interface. a register value = 0 will default to the same effect as register value = 1. sceclk.4 eclkfs.4 sceclk.3 eclkfs.3 sceclk.2 eclkfs.2 sceclk.1 eclkfs.1 sceclk.0 eclkfs.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 parity control register (sparctl): 0xfe11 ? 0x00 this register provides the ability to configure the parity circuitry on the smart card interface. the settings apply to both integrated smart card interfaces. table 95: the sparctl register msb lsb C dispar brkgen brkdet retran discrx inspe forcpe bit symbol function sparctl.7 C sparctl.6 dispar disable parity check C 1 = disabl ed, 0 = enabled. if enabled, the uart will check for even parity (the number of 1s including the parity bit is even) on every character. this also applies to the ts during atr. sparctl.5 brkgen break generation disable C 1 = disabled, 0 = enabled. if enabled, and t=0 protocol, the uart will generate a break to the smart card if a parity error is detected on a receive character. no break will be generated if parity checking is disabled. this also applies to ts during atr. sparctl.4 brkdet break detection disable C 1 = disabled, 0 = enabled. if enabled, and t=0 protocol, the uart will detect the generat ion of a break by the smart card. sparctl.3 retran retransmit byte C 1 = enabled, 0 = disabled. if enabled and a break is detected from the smart card (break detection must be enabled), the last character will be transmitted again. this bit applies to t=0 protocol. sparctl.2 discrx discard received byte C 1 = enabled, 0 = disabled. if enabled and a parity error is detected (parity checking must be enabled), the last character received will be discarded. this bit applies to t=0 protocol. sparctl.1 inspe insert parity error C 1 = enabled, 0 = disabled. used for test purposes. if enabled, the uart will insert a parity error in every character transmitted by generating odd parity instead of even parity for the character. sparctl.0 forcpe force parity error C 1 = enabled, 0 = disabled. used for test purposes. if enabled, the uart will generate a parity error on a character received from the smart card. 104 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 105 byte control register (sbytectl): 0xfe12 ? 0x2c this register controls the processing of characters and the detection of the ts byte. when receiving, a break is asserted at 10.5 etu after the beginning of the start bit. break from the card is sampled at 11 etu. table 96: the sbytectl register msb lsb C detts dirts brkdur.1 brkdur. 0 C C C bit symbol function sbytectl.7 C sbytectl.6 detts detect ts byte C 1 = next byte is ts, 0 = next byte is not ts. when set, the hardware will treat the next character received as the ts and determine if direct or indirect convention is being used. direct convention is the default used if firmware does not set this bit prior to transmission of ts by the smart card to the firmware. the hardware will check parity and generate a break as defined by the dispar and brkgen bits in the parity control register. this bit is cleared by hardware after ts is received. ts is decoded before being stored in the receive fifo. sbytectl.5 dirts direct mode ts select C 1 = dire ct mode, 0 = indirect mode. set/cleared by hardware when ts is processed indicating either direct/indirect mode of operation. when switching between smart cards, the firmware should write the bit appropriately since this register is not unique to an individual smart card (firmware should keep track of this bit). sbytectl.4 brkdur.1 break duration select C 00 = 1 etu, 01 = 1.5 etu, 10 = 2 etu, 11 = reserved. determines the length of a break signal which is generated when detecting a parity error on a character reception in t=0 mode. sbytectl.3 brkdur.0 sbytectl.2 C sbytectl.1 C sbytectl.0 C downloaded from: http:///
73s1217f data sheet ds_1217f_002 fd control register (fdreg): 0xfe13 ? 0x11 table 97: the fdreg register msb lsb fval.3 fval.2 fval.1 fval.0 dval.3 dval.2 dval.1 dval.0 bit symbol function fdreg.7 fval.3 refer to table 99 . this value is converted per the table to set the divide ratio used to generate the baud rate (etu). default, also used for atr, is 0001 (fi = 372). this value is used by the selected interface. fdreg.6 fval.2 fdreg.5 fval.1 fdreg.4 fval.0 fdreg.3 dval.3 refer to table 99 . this value is used to set the divide ratio used to generate the smart card clk. default, also used for atr, is 0001 (di = 1). fdreg.2 dval.2 fdreg.1 dval.1 fdreg.0 dval.0 this register uses the transmission factors f and d to se t the etu (baud) rate. the values in this register are mapped to the iso 7816 conversion factors as descr ibed below. the clk signal for each interface is created by dividing a high-frequency, intermediate signal (msclk) by 2. the etu baud rate is created by dividing msclk by 2 times the fi/di ratio specifi ed by the codes below. for example, if fi = 0001 and di = 0001, the ratio of fi/di is 372/1. thus, the etu divider is configured to divide by 2 * 372 = 744. the maximum supported f/d ratio is 4096. table 98: divider ratios provided by the etu counter fi (code) 0000 0001 0010 0011 0100 0101 0110 0111 fi (ratio) 372 372 558 744 1116 1488 1860 1860 fclk max 4 5 6 8 12 16 20 20 fi(code) 1000 1001 1010 1011 1100 1101 1110 1111 fi(ratio) 512 512 768 1024 1536 2048 2048 2048 fclk max 5 5 7.5 10 15 20 20 20 di(code) 0000 0001 0010 0011 0100 0101 0110 0111 di(ratio) 1 1 2 4 8 16 32 32 di(code) 1000 1001 1010 1011 1100 1101 1110 1111 di(ratio) 12 20 16 16 16 16 16 16 note: values marked with are not included in the iso definition and arbitrary values have been assigned. the values given below are used by the etu divider to create the etu clock. the entries that are not shaded will result in precise clk/etu per iso requirements. shaded areas are not precise but are within 1% of the target value. 106 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 107 table 99: divider values for the etu clock fi code 0000 0001 0010 0011 0100 0101 di code f d 372 372 558 744 1116 1488 0001 1 744 744 1116 1488 2232 2976 0010 2 372 372 558 744 1116 1488 0011 4 186 186 279 372 558 744 0100 8 93 93 138 186 279 372 1000 12 62 62 93 124 186 248 0101 16 47 47 70 93 140 186 1001 20 37 37 56 74 112 149 0110 32 23 23 35 47 70 93 fi code 0110 1001 1010 1011 1100 1101 di code f d 1860 512 768 1024 1536 2048 0001 1 3720 1024 1536 2048 3072 4096 0010 2 1860 512 768 1024 1536 2048 0011 4 930 256 384 512 768 1024 0100 8 465 128 192 256 384 512 1000 12 310 85 128 171 256 341 0101 16 233 64 96 128 192 256 1001 20 186 51 77 102 154 205 0110 32 116 32 48 64 96 128 downloaded from: http:///
73s1217f data sheet ds_1217f_002 crc ms value registers (crcmsb): 0xfe14 ? 0xff, (crclsb): 0xfe15 ? 0xff table 100: the crcmsb register msb lsb crc.15 crc.14 crc.13 crc.12 crc.11 crc.10 crc.9 crc.8 table 101: the crclsb register msb lsb crc.7 crc.6 crc.5 crc.4 crc.3 crc.2 crc.1 crc.0 the 16-bit crc value forms the tx crc word in tx mode (write value) and the rx crc in rx mode (read value). the initial value of crc to be used when generating a crc to be transmitted at the end of a message (after the last tx byte is sent) when enabled in t=1 mode. should be reloaded at the beginning of every message to be transmitted. when using crc, both crc registers should be initialized to ff. when using lrc the crclsb value register should be loaded to 00. when receiving a message, the firmware should load this with the initia l value and then read this register to get the final value at the end of the message. these regi sters need to be reloaded for each new message to be received. when in lrc mode, bits (7:0) are used and bits (15:8) are undefined. during lrc/crc checking and generation, this register is updated wi th the current value and can be read to aid in debugging. this information will be transmitted to the sm art card using the timing specified by the guard time register. when checking crc/lrc on an in coming message (crc/lrc is checked against the data and crc/lrc), the firmware reads the final value after the message has been received and determines if an error occurred (= 0x1d0f (crc) no error, else error; = 0 (lrc) no error, else error). when a message is received, the crc/lrc is stored in the fifo. the polynomial used to generate and check crc is x 16 + x 12 + x 5 +1. when in indirect convention, t he crc is generated prior to the conversion into indirect convention. when in indirect convent ion, the crc is checked after the conversion out of indirect convention. for a gi ven message, the crc generated (and readable from this register) will be the same whether indirect or direct convention is used to transmit the data to the smart card. the crclsb / crcmsb registers will be updated with crc/lrc whenever bits are being received or transmitted from/to the smart card (even if crcen is not set and in mode t1). they are available to the firmware to use if desired. 108 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 109 block guard time register (bgt): 0xfe16 ? 0x10 this register contains the extra guard time value (egt) most-significant bit. the extra guard time indicates the minimum time between the leading edges of the start bit of consec utive characters. the delay is depends on the t=0/t=1 mode. used in transmit mode. this register also contains the block guard time (bgt) value. block guard time is the minimum time between the leading edge of the start bit of the last character received and the leading edge of the start bit of the first character transmitted. this should not be set less than the character length. the transmission of the first character will be held off until bgt has elapsed regardless of t he tx data and tx/rx control bit timing. table 102: the bgt register msb lsb egt.8 C C bgt.4 bgt.3 bgt.1 bgt.2 bgt.0 bit symbol function bgt.7 egt.8 most-significant bit for 9-bit egt timer. see egt below. bgt.6 C bgt.5 C bgt.4 bgt.4 time in etus between the start bit of t he last received character to start bit of the first character transmitted to t he smart card. default value is 22. bgt.3 bgt.3 bgt.2 bgt.2 bgt.1 bgt.1 bgt.0 bgt.0 extra guard time register (egt): 0xfe17 ? 0x0c this register contains the extra guard time value (egt) least-significant byte. the extra guard time indicates the minimum time between the leading edges of the start bit of cons ecutive characters. the delay depends on the t=0/t=1 mode. used in transmit mode. table 103: the egt register msb lsb egt.7 egt.6 egt.5 egt.4 egt.3 egt.1 egt.2 egt.0 bit function egt.7 time in etus between start bits of consecutive characters. in t=0 mode, the minimum is 1. in t=0, the leading edge of the next start bit may be delayed if there is a break detected from the smart card. default value is 12. in t=0 mode, regardless of the value loaded, the minimum value is 12, and for t=1 mode, the minimum value is 11. egt.6 egt.5 egt.4 egt.3 egt.2 egt.1 egt.0 downloaded from: http:///
73s1217f data sheet ds_1217f_002 block wait time registers (bwtb0): 0xfe1b ? 0x00, (bwtb1): 0xfe1a ? 0x00, (bwtb2): 0xfe19 ? 0x00, (bwtb3): 0xfe18 ? 0x00 table 104: the bwtb0 register msb lsb bwt.7 bwt.6 bwt.5 bwt.4 bwt.3 bwt.1 bwt.2 bwt.0 table 105: the bwtb1 register msb lsb bwt.15 bwt.14 bwt.13 bwt.12 bwt.11 bwt.10 bwt.9 bwt.8 table 106: the bwtb2 register msb lsb bwt.23 bwt.22 bwt.21 bwt.20 bwt.19 bwt.18 bwt.17 bwt.16 table 107: the bwtb3 register msb lsb C C C C bwt.27 bwt.26 bwt.25 bwt.24 these registers (bwtb0, bwtb1, bwtb2, bwtb3) are used to set the block waiting time(27:0) (bwt). all of these parameters define the maximum time the 73s1217f will have to wait for a character from the smart card. these registers serve a dual purpose. when t=1, these registers are used to set up the block wait time. the block wait time defines the time in etus between the beginning of the last character sent to smart card and the start bit of t he first character received from smart card. it can be used to detect an unresponsive card and should be loaded by firmware prior to writing the last tx byte. when t = 0, these registers are used to set up the work wait time. the work wait time is defined as the time between the leading edge of two cons ecutive characters being sent to or from the card. if a timeout occurs, an interrupt is generated to the firmware. the firmware can then take appropriate action. a wait time extension (wtx) is supported with the 28-bit bwt. character wait time registers (cwtb0): 0xfe1d ? 0x00, (cwtb1): 0xfe1c ? 0x00 table 108: the cwtb0 register msb lsb cwt.7 cwt.6 cwt.5 cwt.4 cwt.3 cwt.1 cwt.2 cwt.0 table 109: the cwtb1 register msb lsb cwt.15 cwt.14 cwt.13 cwt.12 cwt.11 cwt.10 cwt.9 cwt.8 these registers (cwtb0, cwtb1) are used to hold t he character wait time(15:0) (cwt) or initial waiting time(15:0) (iwt) depending on the situation. both the iwt and the cwt measure the time in etus between the leading edge of the start of the current character received from the smart card and the leading edge of the start of the next character received from the smart card. the only difference is the mode in which the card is operating. when t=1 thes e registers are used to configure the cwt and these registers configure the iwt when the atr is being received. these registers should be loaded prior to receiving characters from the smart card. firmware must manage which time is stored in the register. if a timeout occurs, an interrupt is generated to the fi rmware. the firmware can then take appropriate action. 110 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 111 atr timeout registers (atrlsb): 0xfe20 ? 0x00, (atrmsb): 0xfe1f ? 0x00 table 110: the atrlsb register msb lsb atrto.7 atrto.6 atrto.5 atrto.4 atrto.3 atrto.1 atrto.2 atrto.0 table 111: the atrmsb register msb lsb atrto.15 atrto.14 atrto.13 atrto.12 atrto.11 atrto.10 atrto.9 atrto.8 these registers (atrlsb and atrlsb) form the atr ti meout (atrto [15:0]) parameter. time in etu between the leading edge of the first character and leading edge of the last character of the atr response. timer is enabled when the rcvatr is set and starts when leading edge of the first start bit is received and disabled when the rcvatr is cleared. an atr timeout is generated if this time is exceeded. ts timeout register (ststo): 0xfe21 ? 0x00 table 112: the ststo register msb lsb tst0.7 tst0.6 tst0.5 tst0.4 tst0.3 tst0.1 tst0.2 tst0.0 the ts timeout is the time in etu between the de- assertion of smart card reset and the leading edge of the ts character in the atr (when detts is set). the timer is started when smart card reset is de-asserted. an atr timeout is generated if this time is exceeded (mute card). reset time register (rlength): 0xfe22 ? 0x70 table 113: the rlength register msb lsb rlen.7 rlen.6 rlen.5 rlen.4 rlen.3 rlen.1 rlen.2 rlen.0 time in etus that the hardware delays the de-asse rtion of rst. if set to 0 and rstcrd = 0, the hardware adds no extra delay and the hardware will release rst after vccok is asserted during power-up. if set to 1, it will delay the release of rst by the time in this register. when the firmware sets the rstcrd bit, the hardware will assert reset (rst = 0 on pin). when firmware clears the bit, the hardware will release rst after the delay specified in rlen. if firmware sets the rstcrd bit prior to instructing the power to be applied to the smart ca rd, the hardware will not release rst after power-up until rlen after the firmware clears the rstcrd bit. this provides a means to power up the smart card and hold it in reset until the firmware wants to releas e the rst to the selected smart card. works with the selected smart card interface. downloaded from: http:///
73s1217f data sheet ds_1217f_002 shaded locations indicate functions t hat are not provided in sync mode. table 114: smart card sfr table name address b7 b6 b5 b4 b3 b2 b1 b0 scsel fe00 selsc(1:0) bypass scint fe01 waitto/ rlien crdevt vcctmr rxdavl txevnt txsent txerr rxerr scie fe02 wtoi/ rlien cdevnt vtmren rxdaen txeven txsnten txerr rxerr vccctl fe03 vccsel.1 vccsel.0 vddflt rdyst vccok scpwrdn vcctmr fe04 offtmr(3:0) vcctmr(3:0) crdctl fe05 deboun cdeten detpol puenb pden cardin stxctl fe06 i2cmode txfull txemty txundr lasttx tx/rxb breakd stxdata fe07 txdata(7:0) srxctl fe08 bit9dat lastrx crcerr rxfull rxemty rxovrr paritye srxdata fe09 rxdata(7:0) scctl fe0a rstcrd io iod c8 c4 clklvl clkoff scectl fe0b sio siod sclklvl sclkoff scdir fe0c c8d c4d sprtcol fe0d i2cmode mod9/8b scesyn 0 tmode crcen crcms rcvatr scclk fe0f iclkfs(5:0) sceclk fe10 eclkfs(5:0) sparctl fe11 dispar brkgen brkdet rtran discrx inspe forcpe sbytectl fe12 detts dirts brkdur (1:0) fdreg fe13 fval(3:0) dval (3:0) crcmsb fe14 crc(15:8) crclsb fe15 crc(7:0) bgt fe16 egt8 bgt(4:0) egt fe17 egt(7:0) bwtb3 fe18 bwt(27:24) bwtb2 fe19 bwt(23:16) bwtb1 fe1a bwt(15:8) bwtb0 fe1b bwt(7:0) cwtb1 fe1c cwt(15:8) cwtb0 fe1d cwt(7:0) atrmsb fe1f atrto(15:8) atrlsb fe20 atrto(7:0) ststo fe21 tsto(7:0) rlength fe22 rlen(7:0) 112 rev. 1.2 downloaded from: http:///
ds_1217f_002 73s1217f data sheet rev. 1.2 113 1.7.18 vdd fault detect function the 73s1217f contains a circuit to detect a low-voltage condition on the supply voltage v dd . if enabled, it will deactivate the active inte rnal smart card interface when v dd falls below the v dd fault threshold. the register configures the v dd fault threshold for the nominal default of 2.3v* or a user selectable threshold. the users code may load a different value using t he fovrvddf bit =1 after the power-up cycle has completed vddfault control register (vddfctl): 0xffd4 ? 0x00 table 115: the vddfctl register msb lsb C fovrvddf vddflten C stxdat .3 vddfth.2 vddfth.1 vddfth.0 bit symbol function vddfctl.7 C vddfctl.6 fovrvddf setting this bit high will allow the vddflt (2:0) bits set in this register to control the vddfault threshold. when this bit is set low, the vddfault threshold will be set to the factory default setting of 2.3v*. vddfctl.5 vddflten set = 1 w ill disable vdd fault operation. vddfctl.4 C vddfctl.3 C vddfctl.2 vddfth.2 vdd fault threshold. bit value(2:0) vddfault voltage 000 2.3 (nominal default) 001 2.4 010 2.5 011 2.6 100 2.7 101 2.8 110 2.9 111 3.0 vddfctl.1 vddfth.1 vddfctl.0 vddfth.0 * note: the v dd fault factory default can be set to any thres hold as defined by bits vddfth(2:0). the 73s1217f has the capability to burn fuses at the fact ory to set the factory default to any of these voltages. contact teridian for further details. downloaded from: http:///
73s1217f data sheet ds_1217f_002 114 rev. 1.2 smartcardslot #1 y1 12.000mhz vdd vdd c200.1uf r2 1m + c161uf gnd 1 gnd 2 vpc 3 nc 4 nc 5 nc 6 pres 7 i/o 8 nc 9 aux2 10 aux1 11 gnd 12 clk 13 rst 14 vcc 15 nc 16 vddf_adj 17 scl 18 sda 19 vdd 20 gnd 21 int 22 xtalin 23 xtalout 24 nc 25 i/ouc 26 aux1uc 27 aux2uc 28 sad0 29 sad1 30 sad2 31 nc 32 u3 73s8010r r130 l1 10uh vdd 1 2 bt1battery c1727p c19 1.0uf c1827p + c410uf r1520k vdd 68 reset 1 sec 2 isbr 3 scl 5 sda 6 x32out 7 x32in 8 gnd 9 x12in 10 x12out 11 col0 12 col1 13 col2 14 anain 15 col3 16 rxd 17 txd 18 col4 19 usr7 20 row0 21 row1 22 usr6 23 row2 24 gnd 25 dp 26 dm 27 vdd 28 usr5 29 usr4 30 usr3 31 usr2 32 row3 33 usr1 34 usr0 35 row4 36 row5 37 erst 38 tclk 39 vdd 40 tbus3 41 gnd 42 rxtx 43 tbus2 44 sclk 45 tbus1 46 sio 47 int3 48 int2 49 tbus0 50 test 51 off_req 52 pres 53 vp 54 clk 55 gnd 56 rst 57 vcc 58 c8/aux2 59 c4/aux1 60 i/o 61 vbus 62 on_off 63 vbat 64 vpc 65 lin 66 gnd 67 slug 69 led0 4 u1 73s1217f smartcardslot #2 d1led c120.1uf r73k c11 0.47uf d- 2 d+ 3 gnd 4 vcc 1 gnd 5 gnd 6 j1usb_conn_4 c222pf a 8 . c130.1uf c140.1uf c150.1uf vdd r83k host serial rx + c50.1uf host serial tx down c7 10uf f3 1 y clr 2 vo 3 vdd 2 db0 7 nc 15 gnd 1 rs 4 r/w* 5 e 6 db7 14 db6 13 db5 12 db4 11 db3 10 db2 9 db1 8 u2 de 7 up enter 1 2 s11 sw / b on_off r1 24 f1 1 2 bt4battery 3 30-switchkeypad 9 on/ce x z vdd lcdbrightness adjust c f r4 100k 4 optional lcd display system16 character by 2 lines 1 3 s1sw_mom 5 w usr2 usr1 usr4 usr3 usr5 usr0 0 usr6 6 f2 c1027p r6 1m c10.1uf r91m r5200k c8 4.7uf 1 3 s2sw_mom 1 3 s3sw_mom 1 3 s4sw_mom 1 3 s5 sw_mom r3 24 c927p r1010k 1 3 s6sw_mom 1 3 s12sw_mom 1 3 s17sw_mom 1 3 s22sw_mom 1 3 s27sw_mom r141k 1 3 s7sw_mom 1 3 s13sw_mom 1 3 s18sw_mom 1 3 s23sw_mom 1 3 s28sw_mom 1 3 s8sw_mom d2 5.0v zener 1 3 s14sw_mom 1 3 s19sw_mom c6 0.1uf 1 3 s24sw_mom 1 3 s29sw_mom 1 3 s9sw_mom 1 3 s15sw_mom 1 3 s20sw_mom 3 2 1 q1nfet 1 3 s25sw_mom 1 3 s30sw_mom 1 3 s16 sw_mom 1 3 s10 sw_mom 1 3 s21 sw_mom 1 3 s26 sw_mom 1 3 s31 sw_mom 1 2 bt2battery 1 2 bt3battery d- +5vdc d+ gnd vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j2 smart card connector c322pf usr1 usr2 usr6 usr5 usr4 aa usr3 aa aa r11 0 vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j3 smart card connector vdd r1220k usr0 1 3 2 cw rv1 10k usr5 2 application schematics 2.1 typical application schematic 1 figure 27: 73s1217f typical application schematic (handheld usb pi npad, with combo usb-bus and self-powered configuration) downloaded from: http:///
d 21 s_1 73s1217f data sheet 7f_002 rev. 1.2 115 y2 12.000mhz vdd r161m l2 10uh + c2410uf vdd 68 reset 1 sec 2 isbr 3 scl 5 sda 6 x32out 7 x32in 8 gnd 9 x12in 10 x12out 11 col0 12 col1 13 col2 14 anain 15 col3 16 rxd 17 txd 18 col4 19 usr7 20 row0 21 row1 22 usr6 23 row2 24 gnd 25 dp 26 dm 27 vdd 28 usr5 29 usr4 30 usr3 31 usr2 32 row3 33 usr1 34 usr0 35 row4 36 row5 37 erst 38 tclk 39 vdd 40 tbus3 41 gnd 42 rxtx 43 tbus2 44 sclk 45 tbus1 46 sio 47 int3 48 int2 49 tbus0 50 test 51 off_req 52 pres 53 vp 54 clk 55 gnd 56 rst 57 vcc 58 c8/aux2 59 c4/aux1 60 i/o 61 vbus 62 on_off 63 vbat 64 vpc 65 lin 66 gnd 67 slug 69 led0 4 u4 73s1217f c31 0.47uf d- 2 d+ 3 gnd 4 vcc 1 gnd 5 gnd 6 j4usb_conn_4 c2222pf c320.1uf c330.1uf c340.1uf vdd + c26 10uf c28 4.7uf r18 24 r2120k vdd c3027p c270.1uf c23 0.1uf r19 24 c2927p r1710k d- +5vdc c25 0.1uf gnd d+ smartcardslot #1 vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j5 smart card connector c2122pf r20 0 vdd r22 20k 2.2 typical application schematic 2 figure 28: 73s1217f typical application schematic (usb transparent reader and usb key configuration) downloaded from: http:///
73s1217f data sheet ds_1217f_001 116 rev. 1.2 3 electrical specification 3.1 absolute maximum ratings operation outside these rating limits may cause per manent damage to the device. the smart card interface pins are protected against short circuits to v cc , ground, and each other. parameter rating dc supply voltage, v dd -0.5 to 4.0 vdc supply voltage v pc -0.5 to 6.6 vdc supply voltage v bus -0.5 to 6.6 vdc supply voltage v bat -0.5 to 6.6 vdc storage temperature -60 to 150 c pin voltage (except card interface) -0.3 to (v dd +0.5) vdc pin voltage (card interface) -0.3 to (v cc +0.5) vdc esd tolerance (except card interface) +/- 2kv esd tolerance (card interface) +/- 7kv pin current 200 ma note: esd testing on smart card pins is hbm condi tion, 3 pulses, each polar ity referenced to ground. note: smart card pins are protected against shor ts between any combinations of smart card pins. 3.2 recommended operating conditions unless otherwise noted all specifications are valid over these temperatur es and supply voltage ranges: parameter rating supply voltage v pc 2.7 to 6.5 vdc supply voltage v bus 4.4 to 5.5 vdc supply voltage v bat 4.0 to 6.5 vdc ambient operating temperature (ta) -40 c to +85 c downloaded from: http:///
ds_1217f_002 73s1217f data sheet 3.3 digital io characteristics these requirements pertain to digital i/o pin types with consideration of the specific pin function and configuration. the row pins have 100k ? pull-ups. symbol parameter conditions min. typ. max. unit voh output level, high ioh = -2ma 0.8 * v dd v dd v off_req pin - i oh = -1ma v dd - 0.45 v vol output level, low iol = 2ma 0 0.3 v off_req pin C iol = 2ma 0.45 v vih input voltage, high 2.7v < vdd <3.6v 1.8 v dd +0.3 v vil input voltage, low 2.7v < vdd <3.6v -0.3 0.6 v reset, on_off,pres pins -0.3 0.8 v ileak leakage current 0 < vin < vdd all output modes disabled, pull-up/downs disabled -5 5 a ipu pull-up current if provided and enabled, vout < 0.1v -5 -3 a ipd pull-down current if provided and enabled, vout > vdd C 0.1v 3 5 a symbol parameter conditions min. typ. max. unit iled led drive current vout = 1.3v, 2.7v < vdd < 3.6v 1.7 3.4 8.5 2 4 10 2.3 4.6 11.5 ma iolkrow keypad row output low current 0.0v < voh < 0.1v when pull-up r is enabled -40 -100 a iolkcol keypad column output high current 0.0v < voh < 0.1v when col. is pulled low -1.5 -3 ma rev. 1.2 117 downloaded from: http:///
73s1217f data sheet ds_1217f_002 118 rev. 1.2 3.4 oscillator interface requirements symbol parameter condition min typ. max unit low-power oscillator requirements. no external load beside the crystal and capacitor is permitted on xout32 pxtal power in crystal 1 w iil input leakage current gnd < vin < vdd -5 5 a high-frequency oscillator (xin) parameters. xin is used as input for external clock for test purposes only. a resistor connecting x12in to x12out is required, value = 1m ? vilx12in input low voltage C x12in -0.3 0.3*vdd v vihx12in input high voltage C x12in 0.7*vdd vdd+.0.3 v iilxtal input current -x12in gnd < vin < vdd -10 10 a fxtal crystal resonant frequency fundamental mode 6 12 mhz 3.5 dc characteristics: analog input symbol parameter condition min typ. max unit v thtol voltage threshold tolerance selected threshold value -3% +3% v downloaded from: http:///
ds_1217f_002 73s1217f data sheet 3.6 usb interface requirements parameter condition min typ. max unit receiver parameters differential input sensitivit y vdi |(dp)-(dm)| 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 v single ended receiver threshold vse 0.8 2.0 v transmitter levels low level output voltage vol usbcon = 1 (dp pullup enabled) 0.3 v high level output voltage voh 15k ? resistor to ground vdd C 0.1v vdd v output resistance (1) driver output resistance zdrv steady state drive 1 28 44 ? pd pullup resistor (to vdd) zpu usbcon = 1 1.2 1.5 1.8 k ? transceiver power requirements operating supply current(output) ipso outputs enabled 5 ma operating supply current (input) ipsi outputs hi-z 1 ma supply current in powerdown ipdn 10 na supply current in suspend. ipss 10 na 1 external source (series) termination resistors of 24 ? must be included on circuit board. rev. 1.2 119 downloaded from: http:///
73s1217f data sheet ds_1217f_002 120 rev. 1.2 parameter condition min typ. max unit c l = 50pf, series 24 , 1% source termination resistor included rise time usbtr 10% to 90% 4 20 ns fall time usbtf 90% to 10% 4 20 ns rise/fall time matching trfm (usbtr/usbtf) 90 111.11 % output signal crossover voltage vcrs includes vdi range 1.3 2.0 v source jitter to next transition tdj1 measured as in figure 7- 49 of usb 2.0 spec -3.5 3.5 ns source jitter for paired transitions tdj2 measured as in figure 7- 49 of usb 2.0 spec (1) (2) -4 4 ns receiver jitter to next transition tjr1 measure as in figure 7-51 of usb 2.0 spec. characterized but not production tested. -18.5 18.5 ns receiver jitter for paired transitions tjr2 measure as in figure 7-51 of usb 2.0 spec. characterized but not production tested. -9 9 ns source se0 interval of eop teopt figure 7-50 of usb 2.0 spec 160 175 ns receiver seo interval of eop teopr figure 7-50 of usb 2.0 spec. (3) 82 ns (1) for both transitions of differential signaling. (2) excluding first transition from the idle state. (3) must accept as valid eop. downloaded from: http:///
ds_1217f_002 73s1217f data sheet 3.7 smart card interface requirements symbol parameter condition min typ. max unit card power supply (v cc ) regulator general conditions, -40 c < t < 85 c, 4.75v < v pc < 6.0v, 2.7v < v dd < 3.6v v cc card supply voltage including ripple and noise inactive mode -0.1 0.1 v inactive mode, i cc = 1ma -0.1 0.4 v active mode; i cc <65ma; 5v 4.65 5.25 v active mode; i cc < 65ma; 3v 2.85 3.15 v active mode; i cc < 40ma; 1.8v 1.68 1.92 v active mode; single pulse of 100ma for 2 s; 5 volt, fixed load = 25ma 4.6 5.25 v active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma 2.76 3.15 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 5v 4.6 5.25 v active mode; current pulses of 40nas with peak |i cc | <200ma,t <400ns; 3v 2.7 3.15 v active mode; current pulses of 20nas with peak |i cc | <100ma,t <400ns; 1.8v 1.62 1.92 v v ccrip v cc ripple f ripple = 20khz C 200mhz 350 mv i ccmax card supply output current static load current, v cc >1.65 40 ma static load current, v cc >4.6 or 2.7 volts as selected 65 ma i ccf i cc fault current class a, b (5v and 3v) 100 180 ma class c (1.8v) 60 130 v sr vcc slew rate, rise rise rate on activate c = 0.47 f 0.12 .30 0.50 v/ s v sf vcc slew rate, fall fall rate on deactivate, c = 0.47 f 0.15 .30 1.20 v/ s v rdy vcc ready voltage (vccok = 1) 5v operation, vcc rising 4.6 v 3v operation, vcc rising 2.75 v 1.8v operation, vcc rising 1.65 v rev. 1.2 121 downloaded from: http:///
73s1217f data sheet ds_1217f_002 122 rev. 1.2 symbol parameter condition min typ. max unit interface requirements C data signals: i/o, aux1 and aux2 v oh output level, high i oh =0 0.9 * v cc v cc +0.1 v i oh = -40 a 0.75 v cc v cc +0.1 v v ol output level, low i ol = 1ma 0.15 *v cc v v ih input level, high 0.6 * v cc v cc +0.30 v v il input level, low -0.15 0.2 * v cc v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i leak input leakage v ih = v cc 10 a i il input current, low v il = 0 0.65 ma i il input current, low v il = 0 0.7 ma i shortl short circuit output current for output low, shorted to v cc through 33 15 ma i shorth short circuit output current for output high, shorted to ground through 33 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl = 50pf, 10% to 90%. 100 ns t ir , t if input rise, fall times 1 s r pu internal pull-up resistor output stable for >200ns 8 11 14 k fd max maximum data rate 1 mhz reset and clock for card interface, rst, clk v oh output level, high i oh = -200 a 0.9 * v cc v cc v v ol output level, low i ol = 200 a 0 0.15 * v cc v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i rst_lim output current limit, rst 30 ma i clk_lim output current limit, clk 70 ma t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% 8 ns c l = 200pf for rst, 10% to 90% 100 ns duty cycle for clk c l = 35pf, f clk 20mhz, clkin duty cycle is 48% to 52%. 45 55 % downloaded from: http:///
ds_1217f_002 73s1217f data sheet 3.8 dc characteristics symbol parameter condition min typ. max unit i pc supply current @ v pc = 2.7v (v bus and v bat unconnected) cpu clock @ 24mhz 52 65 78 ma cpu clock @ 12mhz 39 48 58 ma cpu clock @ 6mhz 31 39 46 ma cpu clock @ 3.69mhz 28 35 42 ma supply current @ v pc = 3.3v (v bus and v bat unconnected) cpu clock @ 24mhz 40 50 60 ma cpu clock @ 12mhz 30 37 45 ma cpu clock @ 6mhz 24 30 36 ma cpu clock @ 3.69mhz 22 27 32 ma supply current @ v pc = 5.0v (v bus and v bat unconnected) cpu clock @ 24mhz 24 30 35 ma cpu clock @ 12mhz 18 22 26 ma cpu clock @ 6mhz 14 18 21 ma cpu clock @ 3.69mhz 13 16 19 ma i vbus supply current @ v vbus = 4.4v cpu clock @ 24mhz 19 23 28 ma cpu clock @ 12mhz 14 17 21 ma cpu clock @ 6mhz 11 14 17 ma cpu clock @ 3.69mhz 10 13 15 ma supply current @ v vbus = 5.0v cpu clock @ 24mhz 19 23 28 ma cpu clock @ 12mhz 14 17 21 ma cpu clock @ 6mhz 11 14 17 ma cpu clock @ 3.69mhz 10 13 15 ma supply current @ v vbus = 5.5v cpu clock @ 24mhz 19 23 28 ma cpu clock @ 12mhz 14 17 21 ma cpu clock @ 6mhz 11 14 17 ma cpu clock @ 3.69mhz 10 13 15 ma symbol parameter condition min typ. max unit i vbat supply current @ v vbat = 4.0v (v bus = 0v) cpu clock @ 24mhz 32 40 49 ma cpu clock @ 12mhz 24 30 36 ma cpu clock @ 6mhz 19 24 29 ma cpu clock @ 3.69mhz 17 22 26 ma supply current @ v vbat = cpu clock @ 24mhz 24 30 36 ma rev. 1.2 123 downloaded from: http:///
73s1217f data sheet ds_1217f_002 124 rev. 1.2 5.0v (v bus = 0v) cpu clock @ 12mhz 18 22 27 ma cpu clock @ 6mhz 14 18 21 ma cpu clock @ 3.69mhz 13 16 19 ma supply current @ v vbat = 6.5v (v bus = 0v) cpu clock @ 24mhz 19 23 28 ma cpu clock @ 12mhz 14 17 21 ma cpu clock @ 6mhz 11 14 17 ma cpu clock @ 3.69mhz 10 13 15 ma v dd v dd supply voltage 2.7v < vpc < 6.5v, i vdd < 40ma. 3.0 3.3 3.6 v i dd_in supply current (pins 28 and 40) cpu clock @ 24mhz 29 33.5 ma cpu clock @ 12mhz 21 24 ma cpu clock @ 6mhz 15.5 18 ma cpu clock @ 3.69mhz 13.5 15.5 ma power down (-40 to 85 c) 8 50 a power down (25 c) 6 13 a i dd_out supply current C pin 68 (available to external circuitry) circuit on 20 ma i vbus supply current from v bus v cc off, i ddinternal < 20 a 0.2 0.4 ma i vbat i vpc supply current from v bat or v pc circuit off 0.01 1 a vbus on v bus detection threshold 3.5 v vbus idi s v bus discharge current 50 a external capacitor values c vpc external filter capacitor for v pc 8.0 10.0 12.0 f c vp external filter capacitor for v p 2.0 4.7 10.0 f c vdd * external filter capacitors for v dd 0.2 1.0 f c vcc external filter capacitor for v cc c vcc should be ceramic with low esr (<100m ). 0.2 0.47 1.0 f *note: recommend on 0.1 f for each v dd pin. downloaded from: http:///
ds_1217f_002 73s1217f data sheet 3.9 current fault detection circuits symbol parameter condition min typ. max unit iv pmax v p over current fault 150 ma i ddmax vdd over-current limit 40 100 ma i ccf card overcurrent fault 80 150 ma i ccf1p8 card overcurrent fault v cc = 1.8v 60 130 ma rev. 1.2 125 downloaded from: http:///
73s1217f data sheet ds_1217f_002 126 rev. 1.2 4 equivalent circuits vdd x12lin x12out enable ttl to circuit esd esd figure 29: 12 mhz oscillator circuit vdd x32lin x32out enableb ttl to circuit >1meg esd esd figure 30: 32khz oscillator circuit downloaded from: http:///
ds_1217f_002 73s1217f data sheet pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable esd figure 31: digital i/o circuit pin vdd strong pfet strong nfet data from circuit output disable esd figure 32: digital output circuit rev. 1.2 127 downloaded from: http:///
73s1217f data sheet ds_1217f_002 128 rev. 1.2 pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable very weak pfet esd figure 33: digital i/o with pull up circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable very weak nfet pull-down enable esd figure 34: digital i/o with pull down circuit downloaded from: http:///
ds_1217f_002 73s1217f data sheet pin ttl to circuit esd figure 35: digital input circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable esd very weak pfet very weak nfet pull-down enable esd figure 36: off_req interface circuit rev. 1.2 129 downloaded from: http:///
73s1217f data sheet ds_1217f_002 130 rev. 1.2 pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable 100k ohm esd figure 37: keypad row circuit pin vdd medium pfet strong nfet data from circuit ttl to circuit output disable esd 1200 ohms figure 38: keypad column circuit downloaded from: http:///
ds_1217f_002 73s1217f data sheet pin vdd strong pfet strong nfet data from circuit ttl to circuit pullup disable 0, 2, 4, 10ma current value control esd figure 39: led circuit pin vih>0.7*vdd to circuit logic r= 20k this buffer has a special input threshold: esd figure 40: test and security pin circuit rev. 1.2 131 downloaded from: http:///
73s1217f data sheet ds_1217f_002 132 rev. 1.2 pin to comparator input esd figure 41: analog input circuit pin vcc strong pfet strong nfet from circuit esd esd figure 42: smart card output circuit downloaded from: http:///
ds_1217f_002 73s1217f data sheet 125ns delay io pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 43: smart card i/o circuit pin ttl to circuit very weak nfet pull-down enable esd esd vdd figure 44: pres input circuit rev. 1.2 133 downloaded from: http:///
73s1217f data sheet ds_1217f_002 134 rev. 1.2 dp dm ttl ttl in_pin_n dp_in dm_in rcv_in rp_enb dp_out dm_out zout= 20 zout= 20 output enableb output enableb 1500 vdd esd esd vdd vdd figure 45: usb circuit pin to circuit logic r= 24k esd vpc figure 46: on_off input circuit downloaded from: http:///
ds_1217f_002 73s1217f data sheet 4.1 package pin designation (68-pin qfn) caution: use handling procedures necessary for a static sensitive component teridian 73s1217f col4 usr1 row3 usr3 usr4 usr5 vdd dm dp gnd row2 usr6 row1 row0 usr7 tbus0 test vp vbus clk gnd rst vcc aux2 aux1 io pres on_off vbat lin gnd vdd sec scl sda x32out x32in gnd xi2in x12out col0 col1 col2 ana_in col3 rxd txd int3 sio tbus1 sclk tbus2 rxtx gnd tbus3 vdd tclk erst row5 row4 usr0 isbrreset usr2 int2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 off_req vpc 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 led0 figure 47: 73s1217f pinout figure 47: 73s1217f pinout rev. 1.2 135 downloaded from: http:///
73s1217f data sheet ds_1217f_002 136 rev. 1.2 4.2 packaging information .2 packaging information 68-pin qfn package outline 68-pin qfn package outline notes: 6.3mm x 6.3mm exposed pad area must rema in unconnected (clear of pcb traces or vias). controlling dimensions are in mm. notes: 6.3mm x 6.3mm exposed pad area must rema in unconnected (clear of pcb traces or vias). controlling dimensions are in mm. top view top view seating plane 12 side view 68 12 3 8.00 7.75 8.00 7.75 0.00/0.05 0.2 0.85 0.65 terminal tip for odd terminal/side l c cc 0.40 scale: none section "c-c" 0.20 0.15/0.25 0.00/0.05 bottom view 68 pin#1 id r0.20 0.45 8.00 8.00 6.30 6.15/6.45 0.42 0.24/0.60 0.42 0.24/0.60 6.40 6.40 6.30 6.15/6.45 1 2 3 figure 48: 73s1217f 68 qfn mechanical drawing downloaded from: http:///
ds_1217f_002 73s1217f data sheet 5 ordering information table 116 lists the order numbers and packaging ma rks used to identify 73s1217f products. table 116: order numbers and packaging marks part description order number packaging mark 73s1217f 68-pin qfn, lead free 73s1217f-68im/f 73s1217f68im 73s1217f 68-pin qfn, lead free, tape and reel 73s1217f-imr/f 73s1217f68im 6 related documentation the following 73s1217f documents are available from teridian semiconductor corporation: 73s1217f data sheet (this document) 73s1217f development board quick start guide 73s1217f software development kit quick start guide 73s1217f evaluation board users guide 73s12xxf software users guide 73s12xxf synchronous card design application note 7 contact information for more information about teridian semiconductor produc ts or to check the availability of the 73s1217f, contact us at: 6440 oak canyon road suite 100 irvine, ca 92618-5201 telephone: (714) 508-8800 fax: (714) 508-8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . rev. 1.2 137 downloaded from: http:///
73s1217f data sheet ds_1217f_002 138 rev. 1.2 revision history revision date description 1.0 5/15/2007 first publication. 1.1 11/7/2007 on page 2 , changed bullet from iso-7816 uart 9600 to 115kbps for protocols t=0, t=1 to iso-7816 uart for protocols t=0, t=1. in table 1 , removed nc, pin 44 row. in section 1.4 , changed description to remove pre-boot and 32-cycle references. in section 1.4 , changed the second bullet page zero of flash memory, the preferred location for the users preboot code, may not be page-erased by either mpt or ice. page zero may onl y be erased with global flash erase. note that global flash erase erases xram whether the secure bit is set or not. to page zero of flash me mory may not be page-erased by either mpu or ice. page zero may only be er ased with global flash erase. note that global flash erase erases xram whether the secure bit is set or not. in section 1.7.1 , changed mcount is configured in the mclkctl register must be bound between a value of 1 to 7. the possible crystal or external clock are shown in table 12. to m count is configured in the mclkctl register must be bound between a value of 1 to 7. the possible crystal or external clock frequencies for getting mclk = 96mhz are shown in table 11 . in section 1.7.4 , added depending on the state of the on/off circuitry and power applied to the vbus input, the 73s1217f will go into either standby mode or power off mode. if system power is provided by, vbus or the on/off circuitry is in the on state, the mpu core will placed into standby mode. in the brcon description, changed if bsel = 1, the baud rate is derived using timer 1. to if bsel = 0, the baud rate is derived using timer 1. in section 1.7.15 , removed the following from the emulator port description: the signals of the emul ator port have weak pull-ups. adding resistor footprints for signals e_rs t, e_tclk and e_rxtx on the pcb is recommended. if necessary, adding 10k pull-up resistors on e_tclk and e_rxtx and a 3k on e_rst will help the emulator operate normally if a problem arises. in section 1.7.17.1 , added 230000 to the baud rate selections in bullet 7. in the vccctl description, added the vddflt bit (if enabled) will provide an emergency deactivation of the internal smart card slot. see the vdd fault detect function section for more detail. changed last sentence of the detts bit description from ts is decoded prior to the fifo and is stored in the receive fifo, to ts is decoded before being stored in the receive fifo. in ordering information , removed the leaded part numbers. 1.2 12/16/2008 in table 1 , added more description to the vcc, vpc, vdd, scl, sda, sec, test and pres pins. in section 1.3.2 , changed flsh_erase to erase and flsh_pgadr to pgaddr. a dded the pgaddr register denotes the page address for page erase. the page size is 512 (200h) bytes and there are 128 pages within the flash memory. the pgaddr denotes the upper seven bits of the flash memory address such that bit 7:1 of the pgaddr corresponds to bit 15:9 of the flash memory address. bit 0 of the pgaddr is not used and is ignored. in the description of the downloaded from: http:///
ds_1217f_002 73s1217f data sheet pgaddr register , added note: the page address is shifted left by one bit (see detailed description above). in table 3 , changed flshcrl to flshctl. in table 5 , removed the preboot bit description. in table 5 , moved the trimpctl bit description to fusectl and moved the fusectl bit description to trimpctl. in table 6 , changed pgadr to pgaddr. in table 7 , added pgaddr. in table 8 , changed the reset value for rtcctl from 0x81 to 0x00. added the rtctrim0 and acomp register s. deleted the omp, vrctl, ledcal and lockctl registers. in table 11 , removed mcount entries 7, 8, 9 and 10. in figure 4 , removed cpuclk. in table 22 , corrected the descriptions for tcon.2 and tcon.0. in the miscellaneous control register 1 (misctl1) description, added two paragraphs about mpu clock rates of 12mhz or greater, changing the mpu clock rate or the number of wait states. changed the register address for atrmsb from fe21 to fe1f. in section 1.7.17.5 , deleted the etu clock is held in reset condition until the activation sequence begins (either by vccok=1 or vcctmr timeout) and will go high ? the etu period thereafter. in section 1.7.17.5 , added synchronous card operation is broken down into three primary types. these ar e commonly referred to as 2-wire, 3- wire and i2c synchronous cards. each card type requires different control and timing and therefore requires different algorithms to access. teridian has created an application note to provide detailed algorithms for each card type. refer to the application note titled 73s12xxf synchronous card design application note . in table 85 and table 114 , changed the syckst bit to i2cmode. replaced figure 23 , figure 24 , and figure 25 with new timing diagrams. in table 114 , replaced syckst (stxctl, bit 7) with i2cmode and scisyn (sprtcol, bit 7) with i2cmode. in figure 27 and figure 28 , replaced the schematics with new schematics. in section 3.4 , changed the fxtal min value from 4 to 6. added section 6, related documentation . added section 7, contact information . formatted the document per new standard. added section numbering. rev. 1.2 139 downloaded from: http:///
73s1217f data sheet ds_1217f_002 140 rev. 1.2 ? 2008 teridian semiconductor corpor ation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. windows is a registered trademark of microsoft corporation. signum systems is a trademark of signum systems corporation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the companys warranty detailed in t he teridian semiconductor corporation standard terms and conditions. the company assumes no responsib ility for any errors which may appear in this document, reserves the right to change devices or s pecifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by compar ing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com downloaded from: http:///

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